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broadwell: Add config option to disable DSP power gating in D3 

This is useful for debug and testing.

BUG=chrome-os-partner:29649
BRANCH=None
TEST=build and boot on samus

Original-Change-Id: I9050e75fd7c308ebd97d196298c687f8b0f8f97d
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/210599
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 2831154af4f33717489cb0b62aef228fb8f7c2e2)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: Ie622df02d9ab219cefce5f11332e010b47e3ec6e
Reviewed-on: http://review.coreboot.org/8947
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
This commit is contained in:
Duncan Laurie 2014-07-31 10:41:56 -07:00 committed by Marc Jones
parent 1053f6571c
commit 3ed4d39b57
2 changed files with 18 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
src/soc/intel/broadwell/adsp.c
View File

@ -69,6 +69,15 @@ static void adsp_init(struct device *dev)
/* Set D3 Power Gating Enable in D19:F0:A0 based on PCH type */
tmp32 = pci_read_config32(dev, ADSP_PCI_VDRTCTL0);
if (config->adsp_d3_pg_disable) {
if (pch_is_wpt()) {
tmp32 |= ADSP_VDRTCTL0_D3PGD_WPT;
tmp32 |= ADSP_VDRTCTL0_D3SRAMPGD_WPT;
} else {
tmp32 |= ADSP_VDRTCTL0_D3PGD_LPT;
tmp32 |= ADSP_VDRTCTL0_D3SRAMPGD_LPT;
}
} else {
if (pch_is_wpt()) {
tmp32 &= ~ADSP_VDRTCTL0_D3PGD_WPT;
tmp32 &= ~ADSP_VDRTCTL0_D3SRAMPGD_WPT;
@ -76,6 +85,7 @@ static void adsp_init(struct device *dev)
tmp32 &= ~ADSP_VDRTCTL0_D3PGD_LPT;
tmp32 &= ~ADSP_VDRTCTL0_D3SRAMPGD_LPT;
}
}
pci_write_config32(dev, ADSP_PCI_VDRTCTL0, tmp32);
/* Set PSF Snoop to SA, RCBA+0x3350[10]=1b */

3
src/soc/intel/broadwell/chip.h
View File

@ -84,6 +84,9 @@ struct soc_intel_broadwell_config {
uint8_t sio_i2c0_voltage;
uint8_t sio_i2c1_voltage;
/* Disable ADSP power gating in D3 */
uint8_t adsp_d3_pg_disable;
/*
* Clock Disable Map:
* [21:16] = CLKOUT_PCIE# 5-0