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mb/siemens/mc_ehl1: Adjust USB port settings in devicetree 

There are in total three USB ports that are used on mc_ehl1:
 - Port 1: Type A connector connected to USB2/USB3 port 0
 - Port 2: Type A connector connected to USB2/USB3 port 1
 - Onboard: connected to USB2 port 2
None of the ports supports overcurrent reporting.

Adjust the appropriate UPDs in devicetree to match the hardware
configuration.

Change-Id: I220637b8e9f03efccacd0955e82cfc0c7a6f53ee
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56454
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Werner Zeh 2021-07-20 12:48:12 +02:00 committed by Patrick Georgi
parent 9e57ed642d
commit 3ee18cefa3
1 changed files with 14 additions and 14 deletions
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28
src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb
View File

@ -21,21 +21,21 @@ chip soc/intel/elkhartlake
register "Heci2Enable" = "1" register "Heci2Enable" = "1"
# USB related UPDs # USB related UPDs
register "usb2_ports[0]" = "USB2_PORT_MID(OC3)" # USB3/2 Type A port1 register "usb2_ports[0]" = "USB2_PORT_SHORT(OC_SKIP)" # USB3/2 Type A port 1
register "usb2_ports[1]" = "USB2_PORT_MID(OC3)" # USB2 WWAN register "usb2_ports[1]" = "USB2_PORT_SHORT(OC_SKIP)" # USB3/2 Type A Port 2
register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # USB2 Bluetooth register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Onboard USB
register "usb2_ports[3]" = "USB2_PORT_MID(OC3)" # Type-C Port1 register "usb2_ports[3]" = "USB2_PORT_EMPTY" # Port is unused
register "usb2_ports[4]" = "USB2_PORT_MID(OC3)" # Type-C Port2 register "usb2_ports[4]" = "USB2_PORT_EMPTY" # Port is unused
register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Type-C Port3 register "usb2_ports[5]" = "USB2_PORT_EMPTY" # Port is unused
register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Type-C Port4 register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Port is unused
register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # USB3/2 Type A port2 register "usb2_ports[7]" = "USB2_PORT_EMPTY" # Port is unused
register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # USB2 Type A port1 register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Port is unused
register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # USB2 Type A port2 register "usb2_ports[9]" = "USB2_PORT_EMPTY" # Port is unused
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC3)" # USB3/2 Type A port1 register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port1
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC3)" # USB3/2 Type A port2 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port2
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)" # USB3 WLAN register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Port is not used
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" # UNUSED register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Port is not used
# Skip the CPU repalcement check # Skip the CPU repalcement check
register "SkipCpuReplacementCheck" = "1" register "SkipCpuReplacementCheck" = "1"