vc/amd/agesa/f.../Proc/Mem/Tech/DDR3: Support XMP memory profiles

Add XMP memory profiles support that has been tested on f15tn (A88XM-E)
and f16kb (AM1I-A) with two Crucial BLT8G3D1869DT1TX0, XMP 1 profile.
Added using the datasheets from https://github.com/mikebdp2/ddr3spd :
JEDEC_DDR3_SPD_4_01_02_11R24.pdf and Intel_XMP_Spec_Rev1.1.pdf

Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: I584416e3376afdf377a11783e55c5e9ff41e6b0d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40488
Reviewed-by: Lance Zhao
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/vendorcode/amd/Kconfig

@@ -30,6 +30,10 @@ config CPU_AMD_AGESA_OPENSOURCE
 
 endchoice
 
+if CPU_AMD_AGESA_OPENSOURCE
+source "src/vendorcode/amd/agesa/Kconfig"
+endif
+
 if CPU_AMD_AGESA_BINARY_PI
 source "src/vendorcode/amd/pi/Kconfig"
 endif

src/vendorcode/amd/agesa/Kconfig

@@ -0,0 +1,28 @@
+# SPDX-License-Identifier: GPL-2.0-only
+# This file is part of the coreboot project.
+
+choice
+	prompt "DDR3 memory profile"
+	default CPU_AMD_AGESA_OPENSOURCE_MEM_JEDEC
+	help
+	  Choose the DDR3 memory profile to use for your RAM sticks, e.g. XMP 1.
+	  XMP support is experimental, and your PC will fail booting if you choose
+	  a profile which does not exist on ANY of your RAM sticks! If in doubt
+	  check their SPD Data using a coreboot's great fork of memtest86+ 5.01.
+
+config CPU_AMD_AGESA_OPENSOURCE_MEM_JEDEC
+	bool "JEDEC"
+	help
+	  JEDEC memory profile, standard and stable. Is guaranteed to be working.
+
+config CPU_AMD_AGESA_OPENSOURCE_MEM_XMP_1
+	bool "XMP 1"
+	help
+	  XMP 1 memory profile. Check that it exists on ALL of your RAM sticks!
+
+config CPU_AMD_AGESA_OPENSOURCE_MEM_XMP_2
+	bool "XMP 2"
+	help
+	  XMP 2 memory profile. Check that it exists on ALL of your RAM sticks!
+
+endchoice

src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.h

@@ -95,6 +95,8 @@
 
 #define SPD_FTB          9
 
+#if CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_JEDEC)
+
 #define SPD_DIVIDENT    10
 #define SPD_DIVISOR     11
 
@@ -103,18 +105,70 @@
 #define SPD_CASHI       15
 #define SPD_TAA         16
 
-#define SPD_TRP         20
-#define SPD_TRRD        19
-#define SPD_TRCD        18
-#define SPD_TRAS        22
 #define SPD_TWR         17
+#define SPD_TRCD        18
+#define SPD_TRRD        19
+#define SPD_TRP         20
+#define SPD_UPPER_TRC   21    /* bits 7:4 */
+#define SPD_UPPER_TRAS  21    /* bits 3:0 */
+#define SPD_TRAS        22
+#define SPD_TRC         23
 #define SPD_TWTR        26
 #define SPD_TRTP        27
-#define SPD_TRC         23
+#define SPD_UPPER_TFAW  28    /* bits 3:0 */
-#define SPD_UPPER_TRC   21              /* bit 7:4 */
-#define SPD_UPPER_TRAS  21              /* bit 3:0 */
 #define SPD_TFAW        29
-#define SPD_UPPER_TFAW  28              /* bit 3:0 */
+
+#endif
+
+#if CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_XMP_1)
+
+#define SPD_DIVIDENT    180
+#define SPD_DIVISOR     181
+
+#define SPD_TCK         186
+#define SPD_CASLO       188
+#define SPD_CASHI       189
+#define SPD_TAA         187
+
+#define SPD_TWR         193
+#define SPD_TRCD        192
+#define SPD_TRRD        202
+#define SPD_TRP         191
+#define SPD_UPPER_TRC   194    /* bits 7:4 */
+#define SPD_UPPER_TRAS  194    /* bits 3:0 */
+#define SPD_TRAS        195
+#define SPD_TRC         196
+#define SPD_TWTR        205
+#define SPD_TRTP        201
+#define SPD_UPPER_TFAW  203    /* bits 3:0 */
+#define SPD_TFAW        204
+
+#endif
+
+#if CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_XMP_2)
+
+#define SPD_DIVIDENT    182
+#define SPD_DIVISOR     183
+
+#define SPD_TCK         221
+#define SPD_CASLO       223
+#define SPD_CASHI       224
+#define SPD_TAA         222
+
+#define SPD_TWR         228
+#define SPD_TRCD        227
+#define SPD_TRRD        237
+#define SPD_TRP         226
+#define SPD_UPPER_TRC   229    /* bits 7:4 */
+#define SPD_UPPER_TRAS  229    /* bits 3:0 */
+#define SPD_TRAS        230
+#define SPD_TRC         231
+#define SPD_TWTR        240
+#define SPD_TRTP        236
+#define SPD_UPPER_TFAW  238    /* bits 3:0 */
+#define SPD_TFAW        239
+
+#endif
 
 #define SPD_TCK_FTB     34
 #define SPD_TAA_FTB     35

src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtspd3.h

@@ -94,6 +94,8 @@
 
 #define SPD_FTB          9
 
+#if CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_JEDEC)
+
 #define SPD_DIVIDENT    10
 #define SPD_DIVISOR     11
 
@@ -102,18 +104,70 @@
 #define SPD_CASHI       15
 #define SPD_TAA         16
 
-#define SPD_TRP         20
-#define SPD_TRRD        19
-#define SPD_TRCD        18
-#define SPD_TRAS        22
 #define SPD_TWR         17
+#define SPD_TRCD        18
+#define SPD_TRRD        19
+#define SPD_TRP         20
+#define SPD_UPPER_TRC   21    /* bits 7:4 */
+#define SPD_UPPER_TRAS  21    /* bits 3:0 */
+#define SPD_TRAS        22
+#define SPD_TRC         23
 #define SPD_TWTR        26
 #define SPD_TRTP        27
-#define SPD_TRC         23
+#define SPD_UPPER_TFAW  28    /* bits 3:0 */
-#define SPD_UPPER_TRC   21              /* bit 7:4 */
-#define SPD_UPPER_TRAS  21              /* bit 3:0 */
 #define SPD_TFAW        29
-#define SPD_UPPER_TFAW  28              /* bit 3:0 */
+
+#endif
+
+#if CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_XMP_1)
+
+#define SPD_DIVIDENT    180
+#define SPD_DIVISOR     181
+
+#define SPD_TCK         186
+#define SPD_CASLO       188
+#define SPD_CASHI       189
+#define SPD_TAA         187
+
+#define SPD_TWR         193
+#define SPD_TRCD        192
+#define SPD_TRRD        202
+#define SPD_TRP         191
+#define SPD_UPPER_TRC   194    /* bits 7:4 */
+#define SPD_UPPER_TRAS  194    /* bits 3:0 */
+#define SPD_TRAS        195
+#define SPD_TRC         196
+#define SPD_TWTR        205
+#define SPD_TRTP        201
+#define SPD_UPPER_TFAW  203    /* bits 3:0 */
+#define SPD_TFAW        204
+
+#endif
+
+#if CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_XMP_2)
+
+#define SPD_DIVIDENT    182
+#define SPD_DIVISOR     183
+
+#define SPD_TCK         221
+#define SPD_CASLO       223
+#define SPD_CASHI       224
+#define SPD_TAA         222
+
+#define SPD_TWR         228
+#define SPD_TRCD        227
+#define SPD_TRRD        237
+#define SPD_TRP         226
+#define SPD_UPPER_TRC   229    /* bits 7:4 */
+#define SPD_UPPER_TRAS  229    /* bits 3:0 */
+#define SPD_TRAS        230
+#define SPD_TRC         231
+#define SPD_TWTR        240
+#define SPD_TRTP        236
+#define SPD_UPPER_TFAW  238    /* bits 3:0 */
+#define SPD_TFAW        239
+
+#endif
 
 #define SPD_TCK_FTB     34
 #define SPD_TAA_FTB     35

src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtspd3.h

@@ -95,6 +95,8 @@
 
 #define SPD_FTB          9
 
+#if CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_JEDEC)
+
 #define SPD_DIVIDENT    10
 #define SPD_DIVISOR     11
 
@@ -103,18 +105,82 @@
 #define SPD_CASHI       15
 #define SPD_TAA         16
 
-#define SPD_TRP         20
-#define SPD_TRRD        19
-#define SPD_TRCD        18
-#define SPD_TRAS        22
 #define SPD_TWR         17
+#define SPD_TRCD        18
+#define SPD_TRRD        19
+#define SPD_TRP         20
+#define SPD_UPPER_TRC   21    /* bits 7:4 */
+#define SPD_UPPER_TRAS  21    /* bits 3:0 */
+#define SPD_TRAS        22
+#define SPD_TRC         23
+
+#define SPD_TRFC_LO     24
+#define SPD_TRFC_HI     25
+
 #define SPD_TWTR        26
 #define SPD_TRTP        27
-#define SPD_TRC         23
+#define SPD_UPPER_TFAW  28    /* bits 3:0 */
-#define SPD_UPPER_TRC   21              /* bit 7:4 */
-#define SPD_UPPER_TRAS  21              /* bit 3:0 */
 #define SPD_TFAW        29
-#define SPD_UPPER_TFAW  28              /* bit 3:0 */
+
+#endif
+
+#if CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_XMP_1)
+
+#define SPD_DIVIDENT    180
+#define SPD_DIVISOR     181
+
+#define SPD_TCK         186
+#define SPD_CASLO       188
+#define SPD_CASHI       189
+#define SPD_TAA         187
+
+#define SPD_TWR         193
+#define SPD_TRCD        192
+#define SPD_TRRD        202
+#define SPD_TRP         191
+#define SPD_UPPER_TRC   194    /* bits 7:4 */
+#define SPD_UPPER_TRAS  194    /* bits 3:0 */
+#define SPD_TRAS        195
+#define SPD_TRC         196
+
+#define SPD_TRFC_LO     199
+#define SPD_TRFC_HI     200
+
+#define SPD_TWTR        205
+#define SPD_TRTP        201
+#define SPD_UPPER_TFAW  203    /* bits 3:0 */
+#define SPD_TFAW        204
+
+#endif
+
+#if CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_XMP_2)
+
+#define SPD_DIVIDENT    182
+#define SPD_DIVISOR     183
+
+#define SPD_TCK         221
+#define SPD_CASLO       223
+#define SPD_CASHI       224
+#define SPD_TAA         222
+
+#define SPD_TWR         228
+#define SPD_TRCD        227
+#define SPD_TRRD        237
+#define SPD_TRP         226
+#define SPD_UPPER_TRC   229    /* bits 7:4 */
+#define SPD_UPPER_TRAS  229    /* bits 3:0 */
+#define SPD_TRAS        230
+#define SPD_TRC         231
+
+#define SPD_TRFC_LO     234
+#define SPD_TRFC_HI     235
+
+#define SPD_TWTR        240
+#define SPD_TRTP        236
+#define SPD_UPPER_TFAW  238    /* bits 3:0 */
+#define SPD_TFAW        239
+
+#endif
 
 #define SPD_TCK_FTB     34
 #define SPD_TAA_FTB     35
@@ -122,9 +188,6 @@
 #define SPD_TRP_FTB     37
 #define SPD_TRC_FTB     38
 
-#define SPD_TRFC_LO     24
-#define SPD_TRFC_HI     25
-
 /*-----------------------------
  * Jedec DDR II related equates
  *-----------------------------