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mb/google/dedede/var/pirika: Add USB2 PHY parameters for Type-A/Type-C 

This change are added fine-tuned USB2 PHY parameters to improve the
USB2 eye diagram result.

BUG=b:296493887
BRANCH=firmware-dedede-13606.B
TEST=Local build bios successfully.
     And verified the USB2 eye diagram test result.

Change-Id: I915fe689883267901e8faba28632345d8c227c28
Signed-off-by: Daniel_Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77359
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Daniel_Peng 2023-08-22 10:07:54 +08:00 committed by Eric Lai
parent 16a01d9f34
commit 3eed673659
1 changed files with 11 additions and 1 deletions
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12
src/mainboard/google/dedede/variants/pirika/overridetree.cb
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@ -51,12 +51,22 @@ chip soc/intel/jasperlake
}" }"
# USB Port Configuration # USB Port Configuration
register "usb2_ports[0]" = "{
.enable = 1,
.ocpin = OC_SKIP,
.tx_bias = USB2_BIAS_0MV,
.tx_emp_enable = USB2_DE_EMP_ON_PRE_EMP_ON,
.pre_emp_bias = USB2_BIAS_28P15MV,
.pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
}" # Type-C Port C0
register "usb2_ports[2]" = "{ register "usb2_ports[2]" = "{
.enable = 1, .enable = 1,
.ocpin = OC_SKIP, .ocpin = OC_SKIP,
.tx_bias = USB2_BIAS_0MV,
.tx_emp_enable = USB2_DE_EMP_ON_PRE_EMP_ON,
.pre_emp_bias = USB2_BIAS_28P15MV, .pre_emp_bias = USB2_BIAS_28P15MV,
.pre_emp_bit = USB2_HALF_BIT_PRE_EMP, .pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
}" # Type-A }" # Type-A Port A0
register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Camera register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Camera
register "usb2_ports[7]" = "{ register "usb2_ports[7]" = "{
.enable = 1, .enable = 1,