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nb/intel/haswell/memmap.h: Define MMIO window sizes 

Add defines for the sizes of northbridge MMIO windows and use them where
applicable. The macro names have been taken from Broadwell.

Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical.

Change-Id: I845cba8acbd478cd325d2e364138336d985f9c34
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55479
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Angel Pons 2021-06-14 09:23:40 +02:00 committed by Patrick Georgi
parent 1515a48cff
commit 3eeefba6a0
3 changed files with 20 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
src/northbridge/intel/haswell/acpi/hostbridge.asl
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@ -1,5 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
#include <northbridge/intel/haswell/memmap.h>
Name (_HID, EISAID ("PNP0A08")) // PCIe Name (_HID, EISAID ("PNP0A08")) // PCIe
Name (_CID, EISAID ("PNP0A03")) // PCI Name (_CID, EISAID ("PNP0A03")) // PCI
@ -173,9 +175,9 @@ Device (PDRC)
Name (PDRS, ResourceTemplate () { Name (PDRS, ResourceTemplate () {
Memory32Fixed (ReadWrite, CONFIG_FIXED_RCBA_MMIO_BASE, CONFIG_RCBA_LENGTH) Memory32Fixed (ReadWrite, CONFIG_FIXED_RCBA_MMIO_BASE, CONFIG_RCBA_LENGTH)
Memory32Fixed (ReadWrite, CONFIG_FIXED_MCHBAR_MMIO_BASE, 0x00008000) Memory32Fixed (ReadWrite, CONFIG_FIXED_MCHBAR_MMIO_BASE, MCH_BASE_SIZE)
Memory32Fixed (ReadWrite, CONFIG_FIXED_DMIBAR_MMIO_BASE, 0x00001000) Memory32Fixed (ReadWrite, CONFIG_FIXED_DMIBAR_MMIO_BASE, DMI_BASE_SIZE)
Memory32Fixed (ReadWrite, CONFIG_FIXED_EPBAR_MMIO_BASE, 0x00001000) Memory32Fixed (ReadWrite, CONFIG_FIXED_EPBAR_MMIO_BASE, EP_BASE_SIZE)
Memory32Fixed (ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH) Memory32Fixed (ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH)
Memory32Fixed (ReadWrite, 0xfed20000, 0x00020000) // TXT Memory32Fixed (ReadWrite, 0xfed20000, 0x00020000) // TXT
Memory32Fixed (ReadWrite, 0xfed40000, 0x00005000) // TPM Memory32Fixed (ReadWrite, 0xfed40000, 0x00005000) // TPM

10
src/northbridge/intel/haswell/memmap.h
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@ -3,6 +3,16 @@
#ifndef NORTHBRIDGE_INTEL_HASWELL_MEMMAP_H #ifndef NORTHBRIDGE_INTEL_HASWELL_MEMMAP_H
#define NORTHBRIDGE_INTEL_HASWELL_MEMMAP_H #define NORTHBRIDGE_INTEL_HASWELL_MEMMAP_H
#define MCH_BASE_SIZE 0x8000
#define DMI_BASE_SIZE 0x1000
#define EP_BASE_SIZE 0x1000
#define EDRAM_BASE_SIZE 0x4000
#define GDXC_BASE_SIZE 0x1000
#define GFXVT_BASE_ADDRESS 0xfed90000ULL #define GFXVT_BASE_ADDRESS 0xfed90000ULL
#define GFXVT_BASE_SIZE 0x1000 #define GFXVT_BASE_SIZE 0x1000

12
src/northbridge/intel/haswell/northbridge.c
View File

@ -85,15 +85,13 @@ struct fixed_mmio_descriptor {
const char *description; const char *description;
}; };
#define SIZE_KB(x) ((x) * 1024)
struct fixed_mmio_descriptor mc_fixed_resources[] = { struct fixed_mmio_descriptor mc_fixed_resources[] = {
{ MCHBAR, SIZE_KB(32), get_bar, "MCHBAR" }, { MCHBAR, MCH_BASE_SIZE, get_bar, "MCHBAR" },
{ DMIBAR, SIZE_KB(4), get_bar, "DMIBAR" }, { DMIBAR, DMI_BASE_SIZE, get_bar, "DMIBAR" },
{ EPBAR, SIZE_KB(4), get_bar, "EPBAR" }, { EPBAR, EP_BASE_SIZE, get_bar, "EPBAR" },
{ GDXCBAR, SIZE_KB(4), get_bar_in_mchbar, "GDXCBAR" }, { GDXCBAR, GDXC_BASE_SIZE, get_bar_in_mchbar, "GDXCBAR" },
{ EDRAMBAR, SIZE_KB(16), get_bar_in_mchbar, "EDRAMBAR" }, { EDRAMBAR, EDRAM_BASE_SIZE, get_bar_in_mchbar, "EDRAMBAR" },
}; };
#undef SIZE_KB
/* Add all known fixed MMIO ranges that hang off the host bridge/memory controller device. */ /* Add all known fixed MMIO ranges that hang off the host bridge/memory controller device. */
static void mc_add_fixed_mmio_resources(struct device *dev) static void mc_add_fixed_mmio_resources(struct device *dev)