soc/intel/skylake: Move power_state functions to pmutil.c
This change moves soc_fill_power_state and soc_prev_sleep_state to pmutil.c. It allows the functions to be used across romstage and smm. BUG=b:67874513 Change-Id: I375ac029520c2cdd52926f3ab3c2d5559936dd8c Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22085 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -21,6 +21,7 @@
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#define __SIMPLE_DEVICE__
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#include <arch/acpi.h>
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#include <arch/io.h>
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#include <device/device.h>
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#include <device/pci.h>
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@ -247,3 +248,70 @@ int vbnv_cmos_failed(void)
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{
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return rtc_failure();
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}
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/* Return 0, 3, or 5 to indicate the previous sleep state. */
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int soc_prev_sleep_state(const struct chipset_power_state *ps,
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int prev_sleep_state)
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{
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/*
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* Check for any power failure to determine if this a wake from
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* S5 because the PCH does not set the WAK_STS bit when waking
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* from a true G3 state.
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*/
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if (!(ps->pm1_sts & WAK_STS) &&
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(ps->gen_pmcon_b & (PWR_FLR | SUS_PWR_FLR)))
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prev_sleep_state = ACPI_S5;
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/*
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* If waking from S3 determine if deep S3 is enabled. If not,
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* need to check both deep sleep well and normal suspend well.
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* Otherwise just check deep sleep well.
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*/
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if (prev_sleep_state == ACPI_S3) {
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/* PWR_FLR represents deep sleep power well loss. */
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uint32_t mask = PWR_FLR;
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/* If deep s3 isn't enabled check the suspend well too. */
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if (!deep_s3_enabled())
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mask |= SUS_PWR_FLR;
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if (ps->gen_pmcon_b & mask)
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prev_sleep_state = ACPI_S5;
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}
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return prev_sleep_state;
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}
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void soc_fill_power_state(struct chipset_power_state *ps)
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{
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uint16_t tcobase;
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uint8_t *pmc;
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tcobase = smbus_tco_regs();
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ps->tco1_sts = inw(tcobase + TCO1_STS);
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ps->tco2_sts = inw(tcobase + TCO2_STS);
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printk(BIOS_DEBUG, "TCO_STS: %04x %04x\n",
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ps->tco1_sts, ps->tco2_sts);
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ps->gen_pmcon_a = pci_read_config32(PCH_DEV_PMC, GEN_PMCON_A);
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ps->gen_pmcon_b = pci_read_config32(PCH_DEV_PMC, GEN_PMCON_B);
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pmc = pmc_mmio_regs();
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ps->gblrst_cause[0] = read32(pmc + GBLRST_CAUSE0);
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ps->gblrst_cause[1] = read32(pmc + GBLRST_CAUSE1);
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printk(BIOS_DEBUG, "GEN_PMCON: %08x %08x\n",
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ps->gen_pmcon_a, ps->gen_pmcon_b);
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printk(BIOS_DEBUG, "GBLRST_CAUSE: %08x %08x\n",
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ps->gblrst_cause[0], ps->gblrst_cause[1]);
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}
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int acpi_get_sleep_type(void)
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{
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struct chipset_power_state *ps;
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ps = pmc_get_power_state();
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return ps->prev_sleep_state;
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}
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@ -1,8 +1,5 @@
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verstage-y += power_state.c
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romstage-$(CONFIG_PLATFORM_USES_FSP1_1) += car_stage.S
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romstage-y += pmc.c
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romstage-y += power_state.c
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romstage-$(CONFIG_PLATFORM_USES_FSP1_1) += romstage.c
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romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage_fsp20.c
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romstage-y += systemagent.c
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@ -1,103 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2014 Google Inc.
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* Copyright (C) 2015 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/acpi.h>
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#include <arch/io.h>
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#include <cbmem.h>
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_def.h>
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#include <reg_script.h>
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#include <stdint.h>
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#include <stdlib.h>
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#include <string.h>
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#include <soc/iomap.h>
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#include <soc/smbus.h>
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#include <soc/pci_devs.h>
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#include <soc/pm.h>
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#include <soc/pmc.h>
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#include <soc/romstage.h>
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#include <vboot/vboot_common.h>
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#include <intelblocks/pmclib.h>
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/* Return 0, 3, or 5 to indicate the previous sleep state. */
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int soc_prev_sleep_state(const struct chipset_power_state *ps,
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int prev_sleep_state)
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{
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/*
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* Check for any power failure to determine if this a wake from
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* S5 because the PCH does not set the WAK_STS bit when waking
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* from a true G3 state.
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*/
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if (!(ps->pm1_sts & WAK_STS) &&
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(ps->gen_pmcon_b & (PWR_FLR | SUS_PWR_FLR)))
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prev_sleep_state = ACPI_S5;
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/*
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* If waking from S3 determine if deep S3 is enabled. If not,
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* need to check both deep sleep well and normal suspend well.
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* Otherwise just check deep sleep well.
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*/
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if (prev_sleep_state == ACPI_S3) {
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/* PWR_FLR represents deep sleep power well loss. */
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uint32_t mask = PWR_FLR;
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/* If deep s3 isn't enabled check the suspend well too. */
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if (!deep_s3_enabled())
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mask |= SUS_PWR_FLR;
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if (ps->gen_pmcon_b & mask)
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prev_sleep_state = ACPI_S5;
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}
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return prev_sleep_state;
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}
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void soc_fill_power_state(struct chipset_power_state *ps)
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{
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uint16_t tcobase;
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uint8_t *pmc;
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tcobase = smbus_tco_regs();
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ps->tco1_sts = inw(tcobase + TCO1_STS);
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ps->tco2_sts = inw(tcobase + TCO2_STS);
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printk(BIOS_DEBUG, "TCO_STS: %04x %04x\n",
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ps->tco1_sts, ps->tco2_sts);
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ps->gen_pmcon_a = pci_read_config32(PCH_DEV_PMC, GEN_PMCON_A);
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ps->gen_pmcon_b = pci_read_config32(PCH_DEV_PMC, GEN_PMCON_B);
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pmc = pmc_mmio_regs();
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ps->gblrst_cause[0] = read32(pmc + GBLRST_CAUSE0);
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ps->gblrst_cause[1] = read32(pmc + GBLRST_CAUSE1);
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printk(BIOS_DEBUG, "GEN_PMCON: %08x %08x\n",
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ps->gen_pmcon_a, ps->gen_pmcon_b);
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printk(BIOS_DEBUG, "GBLRST_CAUSE: %08x %08x\n",
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ps->gblrst_cause[0], ps->gblrst_cause[1]);
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}
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int acpi_get_sleep_type(void)
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{
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struct chipset_power_state *ps;
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ps = pmc_get_power_state();
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return ps->prev_sleep_state;
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}
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