nb/amd/amdk8: Link reset_test.c

This needs some extra headers in amdk8/raminit.c that were otherwise
provided by that file.

Change-Id: I80450e5eb32eb502b3d777c56790db90491fc995
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19360
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

src/cpu/amd/model_fxx/init_cpus.c

@@ -11,6 +11,8 @@
  * GNU General Public License for more details.
  */
 
+#include <cpu/x86/lapic.h>
+#include <northbridge/amd/amdk8/amdk8.h>
 #include "cpu/amd/car/post_cache_as_ram.c"
 
 #if CONFIG_HAVE_OPTION_TABLE

src/mainboard/amd/dbm690t/romstage.c

@@ -25,7 +25,6 @@
 #include <northbridge/amd/amdk8/raminit.h>
 #include <delay.h>
 #include <cpu/x86/lapic.h>
-#include "northbridge/amd/amdk8/reset_test.c"
 #include <superio/ite/common/ite.h>
 #include <superio/ite/it8712f/it8712f.h>
 #include <spd.h>

src/mainboard/amd/mahogany/romstage.c

@@ -26,7 +26,6 @@
 #include <northbridge/amd/amdk8/raminit.h>
 #include <delay.h>
 #include <cpu/x86/lapic.h>
-#include "northbridge/amd/amdk8/reset_test.c"
 #include <superio/ite/common/ite.h>
 #include <superio/ite/it8718f/it8718f.h>
 #include <cpu/x86/bist.h>

src/mainboard/amd/pistachio/romstage.c

@@ -25,7 +25,6 @@
 #include <northbridge/amd/amdk8/raminit.h>
 #include <delay.h>
 #include <cpu/x86/lapic.h>
-#include "northbridge/amd/amdk8/reset_test.c"
 #include <spd.h>
 #include <cpu/x86/bist.h>
 #include "northbridge/amd/amdk8/setup_resource_map.c"

src/mainboard/amd/serengeti_cheetah/romstage.c

@@ -23,7 +23,6 @@
 #include "southbridge/amd/amd8111/early_smbus.c"
 #include <reset.h>
 #include <northbridge/amd/amdk8/raminit.h>
-#include "northbridge/amd/amdk8/reset_test.c"
 #include <cpu/x86/bist.h>
 #include <delay.h>
 

src/mainboard/asrock/939a785gmh/romstage.c

@@ -27,7 +27,6 @@
 #include <delay.h>
 #include <spd.h>
 #include <cpu/x86/lapic.h>
-#include "northbridge/amd/amdk8/reset_test.c"
 #include <superio/winbond/common/winbond.h>
 #include <superio/winbond/w83627dhg/w83627dhg.h>
 #include <cpu/x86/bist.h>

src/mainboard/asus/a8n_e/romstage.c

@@ -29,7 +29,6 @@
 #include <cpu/x86/lapic.h>
 #include <pc80/mc146818rtc.h>
 #include <cpu/x86/lapic.h>
-#include "northbridge/amd/amdk8/reset_test.c"
 #include <superio/ite/common/ite.h>
 #include <superio/ite/it8712f/it8712f.h>
 #include <cpu/amd/model_fxx_rev.h>

src/mainboard/asus/a8v-e_deluxe/romstage.c

@@ -33,7 +33,6 @@ unsigned int get_sbdn(unsigned bus);
 #include <northbridge/amd/amdk8/raminit.h>
 #include <delay.h>
 #include <cpu/x86/lapic.h>
-#include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 #include <superio/winbond/common/winbond.h>
 #include <superio/winbond/w83627ehg/w83627ehg.h>

src/mainboard/asus/a8v-e_se/romstage.c

@@ -33,7 +33,6 @@ unsigned int get_sbdn(unsigned bus);
 #include <northbridge/amd/amdk8/raminit.h>
 #include <delay.h>
 #include <cpu/x86/lapic.h>
-#include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 #include <superio/winbond/common/winbond.h>
 #include <superio/winbond/w83627ehg/w83627ehg.h>

src/mainboard/asus/k8v-x/romstage.c

@@ -33,7 +33,6 @@ unsigned int get_sbdn(unsigned bus);
 #include <northbridge/amd/amdk8/raminit.h>
 #include <delay.h>
 #include <cpu/x86/lapic.h>
-#include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 #include <superio/winbond/common/winbond.h>
 #include <superio/winbond/w83697hf/w83697hf.h>

src/mainboard/asus/kfsn4-dre_k8/romstage.c

@@ -32,7 +32,6 @@ unsigned int get_sbdn(unsigned bus);
 #include "southbridge/nvidia/ck804/early_smbus.h"
 #include <reset.h>
 #include <northbridge/amd/amdk8/raminit.h>
-#include "northbridge/amd/amdk8/reset_test.c"
 #include <cpu/x86/bist.h>
 #include <delay.h>
 

src/mainboard/asus/m2n-e/romstage.c

@@ -32,7 +32,6 @@
 #include <lib.h>
 #include <spd.h>
 #include <cpu/x86/lapic.h>
-#include "northbridge/amd/amdk8/reset_test.c"
 #include <superio/ite/common/ite.h>
 #include <superio/ite/it8716f/it8716f.h>
 #include <cpu/x86/bist.h>

src/mainboard/asus/m2v-mx_se/romstage.c

@@ -33,7 +33,6 @@ unsigned int get_sbdn(unsigned bus);
 #include <halt.h>
 #include <northbridge/amd/amdk8/raminit.h>
 #include <delay.h>
-#include "northbridge/amd/amdk8/reset_test.c"
 
 #include <superio/ite/common/ite.h>
 #include <superio/ite/it8712f/it8712f.h>

src/mainboard/asus/m2v/romstage.c

@@ -33,7 +33,6 @@ unsigned int get_sbdn(unsigned bus);
 #include <halt.h>
 #include <northbridge/amd/amdk8/raminit.h>
 #include <delay.h>
-#include "northbridge/amd/amdk8/reset_test.c"
 
 #include <superio/ite/common/ite.h>
 #include <superio/ite/it8712f/it8712f.h>

src/mainboard/broadcom/blast/romstage.c

@@ -12,7 +12,6 @@
 #include <northbridge/amd/amdk8/raminit.h>
 #include <delay.h>
 #include <cpu/x86/lapic.h>
-#include "northbridge/amd/amdk8/reset_test.c"
 
 #include <superio/nsc/pc87417/pc87417.h>
 #include <cpu/x86/bist.h>

src/mainboard/gigabyte/ga_2761gxdk/romstage.c

@@ -33,7 +33,6 @@
 #include <northbridge/amd/amdk8/raminit.h>
 #include <delay.h>
 #include <cpu/x86/lapic.h>
-#include "northbridge/amd/amdk8/reset_test.c"
 #include <superio/ite/common/ite.h>
 #include <superio/ite/it8716f/it8716f.h>
 #include <cpu/x86/bist.h>

src/mainboard/gigabyte/m57sli/romstage.c

@@ -30,7 +30,6 @@
 #include <northbridge/amd/amdk8/raminit.h>
 #include <delay.h>
 #include <cpu/x86/lapic.h>
-#include "northbridge/amd/amdk8/reset_test.c"
 #include <superio/ite/common/ite.h>
 #include <superio/ite/it8716f/it8716f.h>
 #include <cpu/x86/bist.h>

src/mainboard/hp/dl145_g1/romstage.c

@@ -15,7 +15,6 @@
 #include <northbridge/amd/amdk8/amdk8.h>
 #include "southbridge/amd/amd8111/early_smbus.c"
 #include <northbridge/amd/amdk8/raminit.h>
-#include "northbridge/amd/amdk8/reset_test.c"
 
 #include <superio/winbond/common/winbond.h>
 #include <superio/winbond/w83627hf/w83627hf.h>

src/mainboard/hp/dl145_g3/romstage.c

@@ -35,7 +35,6 @@
 #include <northbridge/amd/amdk8/raminit.h>
 #include <delay.h>
 #include <cpu/x86/lapic.h>
-#include "northbridge/amd/amdk8/reset_test.c"
 #include <superio/serverengines/pilot/pilot.h>
 #include <superio/nsc/pc87417/pc87417.h>
 #include <cpu/x86/bist.h>

src/mainboard/iwill/dk8_htx/romstage.c

@@ -9,7 +9,6 @@
 #include <cpu/amd/model_fxx_rev.h>
 #include "southbridge/amd/amd8111/early_smbus.c"
 #include <northbridge/amd/amdk8/raminit.h>
-#include "northbridge/amd/amdk8/reset_test.c"
 #include <cpu/x86/bist.h>
 #include <delay.h>
 

src/mainboard/kontron/kt690/romstage.c

@@ -27,7 +27,6 @@
 #include <delay.h>
 #include <spd.h>
 #include <cpu/x86/lapic.h>
-#include "northbridge/amd/amdk8/reset_test.c"
 
 #include <superio/winbond/common/winbond.h>
 #include <superio/winbond/w83627dhg/w83627dhg.h>

src/mainboard/msi/ms7135/romstage.c

@@ -26,7 +26,6 @@
 #include <cpu/x86/lapic.h>
 #include <pc80/mc146818rtc.h>
 #include <cpu/x86/lapic.h>
-#include "northbridge/amd/amdk8/reset_test.c"
 #include <superio/winbond/common/winbond.h>
 #include <superio/winbond/w83627thg/w83627thg.h>
 #include <cpu/amd/model_fxx_rev.h>

src/mainboard/msi/ms7260/romstage.c

@@ -32,7 +32,6 @@
 #include <lib.h>
 #include <spd.h>
 #include <cpu/x86/lapic.h>
-#include "northbridge/amd/amdk8/reset_test.c"
 #include <superio/winbond/common/winbond.h>
 #include <superio/winbond/w83627ehg/w83627ehg.h>
 #include <cpu/x86/bist.h>

src/mainboard/msi/ms9185/romstage.c

@@ -34,7 +34,6 @@
 #include <delay.h>
 #include <reset.h>
 #include <cpu/x86/lapic.h>
-#include "northbridge/amd/amdk8/reset_test.c"
 
 #include <superio/nsc/pc87417/pc87417.h>
 #include <cpu/x86/bist.h>

src/mainboard/msi/ms9282/romstage.c

@@ -31,7 +31,6 @@
 #include <northbridge/amd/amdk8/raminit.h>
 #include <delay.h>
 #include <cpu/x86/lapic.h>
-#include "northbridge/amd/amdk8/reset_test.c"
 
 #include <superio/winbond/common/winbond.h>
 #include <superio/winbond/w83627ehg/w83627ehg.h>

src/mainboard/nvidia/l1_2pvv/romstage.c

@@ -31,7 +31,6 @@
 #include <northbridge/amd/amdk8/raminit.h>
 #include <delay.h>
 #include <cpu/x86/lapic.h>
-#include "northbridge/amd/amdk8/reset_test.c"
 #include <superio/winbond/common/winbond.h>
 #include <superio/winbond/w83627ehg/w83627ehg.h>
 #include <cpu/x86/bist.h>

src/mainboard/siemens/sitemp_g1p1/romstage.c

@@ -30,7 +30,6 @@
 #include <delay.h>
 
 #include <cpu/x86/lapic.h>
-#include "northbridge/amd/amdk8/reset_test.c"
 #include <superio/ite/common/ite.h>
 #include <superio/ite/it8712f/it8712f.h>
 

src/mainboard/sunw/ultra40/romstage.c

@@ -14,7 +14,6 @@
 #include <northbridge/amd/amdk8/raminit.h>
 #include <delay.h>
 #include <cpu/x86/lapic.h>
-#include "northbridge/amd/amdk8/reset_test.c"
 
 #include <superio/smsc/lpc47b397/lpc47b397.h>
 #include <cpu/x86/bist.h>

src/mainboard/sunw/ultra40m2/romstage.c

@@ -31,7 +31,6 @@
 #include <northbridge/amd/amdk8/raminit.h>
 #include <delay.h>
 #include <cpu/x86/lapic.h>
-#include "northbridge/amd/amdk8/reset_test.c"
 #include <superio/smsc/dme1737/dme1737.h>
 #include <cpu/x86/bist.h>
 

src/mainboard/supermicro/h8dme/romstage.c

@@ -28,7 +28,6 @@
 #include <northbridge/amd/amdk8/raminit.h>
 #include <delay.h>
 #include <cpu/x86/lapic.h>
-#include "northbridge/amd/amdk8/reset_test.c"
 #include <superio/winbond/common/winbond.h>
 #include <superio/winbond/w83627hf/w83627hf.h>
 #include <cpu/x86/bist.h>

src/mainboard/supermicro/h8dmr/romstage.c

@@ -31,7 +31,6 @@
 #include <northbridge/amd/amdk8/raminit.h>
 #include <delay.h>
 #include <cpu/x86/lapic.h>
-#include "northbridge/amd/amdk8/reset_test.c"
 #include <superio/winbond/common/winbond.h>
 #include <superio/winbond/w83627hf/w83627hf.h>
 #include <cpu/x86/bist.h>

src/mainboard/technexion/tim5690/romstage.c

@@ -26,7 +26,6 @@
 #include <delay.h>
 #include <spd.h>
 #include <cpu/x86/lapic.h>
-#include "northbridge/amd/amdk8/reset_test.c"
 
 #include <superio/ite/common/ite.h>
 #include <superio/ite/it8712f/it8712f.h>

src/mainboard/technexion/tim8690/romstage.c

@@ -26,7 +26,6 @@
 #include <delay.h>
 #include <spd.h>
 #include <cpu/x86/lapic.h>
-#include "northbridge/amd/amdk8/reset_test.c"
 
 #include <superio/ite/common/ite.h>
 #include <superio/ite/it8712f/it8712f.h>

src/mainboard/tyan/s2912/romstage.c

@@ -31,7 +31,6 @@
 #include <northbridge/amd/amdk8/raminit.h>
 #include <delay.h>
 #include <cpu/x86/lapic.h>
-#include "northbridge/amd/amdk8/reset_test.c"
 #include <superio/winbond/common/winbond.h>
 #include <superio/winbond/w83627hf/w83627hf.h>
 #include <cpu/x86/bist.h>

src/mainboard/winent/mb6047/romstage.c

@@ -14,7 +14,6 @@
 #include <northbridge/amd/amdk8/raminit.h>
 #include <delay.h>
 #include <cpu/x86/lapic.h>
-#include "northbridge/amd/amdk8/reset_test.c"
 #include <superio/winbond/common/winbond.h>
 #include <superio/winbond/w83627thg/w83627thg.h>
 #include <cpu/x86/bist.h>

src/northbridge/amd/amdk8/Makefile.inc

@@ -11,6 +11,8 @@ romstage-$(CONFIG_HAVE_ACPI_RESUME) += exit_from_self.c
 romstage-y += raminit_f.c
 endif
 
+romstage-y += reset_test.c
+
 # Enable this if you want to check the values of the PCI routing registers.
 # Call show_all_routes() anywhere amdk8.h is included.
 #ramstage-y += util.c

src/northbridge/amd/amdk8/amdk8.h

@@ -11,12 +11,21 @@
 	#include "pre_f.h"
 #endif
 
+#define HTIC_ColdR_Detect  (1<<4)
+#define HTIC_BIOSR_Detect  (1<<5)
+#define HTIC_INIT_Detect   (1<<6)
+
 #ifdef __PRE_RAM__
 void showallroutes(int level, pci_devfn_t dev);
 void setup_resource_map_offset(const unsigned int *register_values, int max, unsigned offset_pci_dev, unsigned offset_io_base);
 void fill_mem_ctrl(int controllers, struct mem_controller *ctrl_a, const uint16_t *spd_addr);
 #endif
 
+void set_bios_reset(void);
+void distinguish_cpu_resets(unsigned int nodeid);
+unsigned int get_sblk(void);
+unsigned int get_sbbusn(unsigned sblk);
+
 void cpus_ready_for_init(void);
 
 #endif /* AMDK8_H */

src/northbridge/amd/amdk8/raminit.c

@@ -5,7 +5,9 @@
 */
 
 #include <cpu/x86/cache.h>
+#include <cpu/x86/lapic.h>
 #include <cpu/x86/mtrr.h>
+#include <cpu/x86/msr.h>
 #include <cpu/amd/mtrr.h>
 #include <lib.h>
 #include <stdlib.h>

src/northbridge/amd/amdk8/reset_test.c

@@ -1,10 +1,8 @@
+#include <arch/io.h>
+#include <console/console.h>
 #include <stdint.h>
 #include <cpu/x86/lapic.h>
-#include "raminit.h"
-
-#define HTIC_ColdR_Detect  (1<<4)
-#define HTIC_BIOSR_Detect  (1<<5)
-#define HTIC_INIT_Detect   (1<<6)
+#include "amdk8.h"
 
 static inline int cpu_init_detected(unsigned nodeid)
 {
@@ -33,7 +31,7 @@ static inline int cold_reset_detected(void)
 	return !(htic & HTIC_ColdR_Detect);
 }
 
-static inline void distinguish_cpu_resets(unsigned nodeid)
+void distinguish_cpu_resets(unsigned int nodeid)
 {
 	u32 htic;
 	pci_devfn_t device;
@@ -43,7 +41,6 @@ static inline void distinguish_cpu_resets(unsigned nodeid)
 	pci_io_write_config32(device, HT_INIT_CONTROL, htic);
 }
 
-void set_bios_reset(void);
 void set_bios_reset(void)
 {
 	u32 htic;
@@ -71,7 +68,7 @@ static unsigned node_link_to_bus(unsigned node, unsigned link)
 	return 0;
 }
 
-static inline unsigned get_sblk(void)
+unsigned int get_sblk(void)
 {
 	u32 reg;
 	/* read PCI_DEV(0,0x18,0) 0x64 bit [8:9] to find out SbLink m */
@@ -79,7 +76,7 @@ static inline unsigned get_sblk(void)
 	return ((reg>>8) & 3);
 }
 
-static inline unsigned get_sbbusn(unsigned sblk)
+unsigned int get_sbbusn(unsigned sblk)
 {
 	return node_link_to_bus(0, sblk);
 }