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soc/{amd, intel}: Make use of common postcar_enable_tseg_cache() API 

This patch removes dedicated function call to make TSEG region cache
from soc and refers to postcar_enable_tseg_cache().

BUG=b:140008206

Change-Id: I18a032b43a2093c8ae86735c119d8dfee40570b1
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35025
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Subrata Banik 2019-09-10 15:51:17 +05:30
parent b3426c03b4
commit 3eff037f8c
5 changed files with 10 additions and 55 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
src/soc/amd/picasso/romstage.c
View File

@ -44,8 +44,6 @@ asmlinkage void car_stage_entry(void)
{
struct postcar_frame pcf;
uintptr_t top_of_ram;
uintptr_t smm_base;
size_t smm_size;
int s3_resume = acpi_s3_resume_allowed() && acpi_is_wakeup_s3();
console_init();
@ -87,15 +85,8 @@ asmlinkage void car_stage_entry(void)
/* Cache the memory-mapped boot media. */
postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT);
/*
* Cache the TSEG region at the top of ram. This region is
* not restricted to SMM mode until SMM has been relocated.
* By setting the region to cacheable it provides faster access
* when relocating the SMM handler as well as using the TSEG
* region for other purposes.
*/
smm_region(&smm_base, &smm_size);
postcar_frame_add_mtrr(&pcf, smm_base, smm_size, MTRR_TYPE_WRBACK);
/* Cache the TSEG region */
postcar_enable_tseg_cache(&pcf);
post_code(0x45);
run_postcar_phase(&pcf);

13
src/soc/amd/stoneyridge/romstage.c
View File

@ -85,8 +85,6 @@ asmlinkage void car_stage_entry(void)
{
struct postcar_frame pcf;
uintptr_t top_of_ram;
uintptr_t smm_base;
size_t smm_size;
msr_t base, mask;
msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR);
int vmtrrs = mtrr_cap.lo & MTRR_CAP_VCNT;
@ -172,15 +170,8 @@ asmlinkage void car_stage_entry(void)
/* Cache the memory-mapped boot media. */
postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT);
/*
* Cache the TSEG region at the top of ram. This region is
* not restricted to SMM mode until SMM has been relocated.
* By setting the region to cacheable it provides faster access
* when relocating the SMM handler as well as using the TSEG
* region for other purposes.
*/
smm_region(&smm_base, &smm_size);
postcar_frame_add_mtrr(&pcf, smm_base, smm_size, MTRR_TYPE_WRBACK);
/* Cache the TSEG region */
postcar_enable_tseg_cache(&pcf);
post_code(0x45);
run_postcar_phase(&pcf);

13
src/soc/intel/apollolake/memmap.c
View File

@ -53,8 +53,6 @@ void smm_region(uintptr_t *start, size_t *size)
void fill_postcar_frame(struct postcar_frame *pcf)
{
uintptr_t top_of_ram;
uintptr_t smm_base;
size_t smm_size;
/*
* We need to make sure ramstage will be run cached. At this point exact
@ -67,13 +65,6 @@ void fill_postcar_frame(struct postcar_frame *pcf)
postcar_frame_add_mtrr(pcf, top_of_ram - 16*MiB, 16*MiB,
MTRR_TYPE_WRBACK);
/*
* Cache the TSEG region at the top of ram. This region is
* not restricted to SMM mode until SMM has been relocated.
* By setting the region to cacheable it provides faster access
* when relocating the SMM handler as well as using the TSEG
* region for other purposes.
*/
smm_region(&smm_base, &smm_size);
postcar_frame_add_mtrr(pcf, smm_base, smm_size, MTRR_TYPE_WRBACK);
/* Cache the TSEG region */
postcar_enable_tseg_cache(pcf);
}

13
src/soc/intel/denverton_ns/memmap.c
View File

@ -81,8 +81,6 @@ void smm_region(uintptr_t *start, size_t *size)
void fill_postcar_frame(struct postcar_frame *pcf)
{
uintptr_t top_of_ram;
uintptr_t smm_base;
size_t smm_size;
/*
* We need to make sure ramstage will be run cached. At this point exact
@ -93,13 +91,6 @@ void fill_postcar_frame(struct postcar_frame *pcf)
postcar_frame_add_mtrr(pcf, top_of_ram - 16 * MiB, 16 * MiB,
MTRR_TYPE_WRBACK);
/*
* Cache the TSEG region at the top of ram. This region is
* not restricted to SMM mode until SMM has been relocated.
* By setting the region to cacheable it provides faster access
* when relocating the SMM handler as well as using the TSEG
* region for other purposes.
*/
smm_region(&smm_base, &smm_size);
postcar_frame_add_mtrr(pcf, smm_base, smm_size, MTRR_TYPE_WRBACK);
/* Cache the TSEG region */
postcar_enable_tseg_cache(pcf);
}

13
src/soc/intel/skylake/memmap.c
View File

@ -296,8 +296,6 @@ void *cbmem_top(void)
void fill_postcar_frame(struct postcar_frame *pcf)
{
uintptr_t top_of_ram;
uintptr_t smm_base;
size_t smm_size;
/*
* We need to make sure ramstage will be run cached. At this
@ -310,14 +308,7 @@ void fill_postcar_frame(struct postcar_frame *pcf)
top_of_ram -= 16*MiB;
postcar_frame_add_mtrr(pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK);
/*
* Cache the TSEG region at the top of ram. This region is
* not restricted to SMM mode until SMM has been relocated.
* By setting the region to cacheable it provides faster access
* when relocating the SMM handler as well as using the TSEG
* region for other purposes.
*/
smm_region(&smm_base, &smm_size);
postcar_frame_add_mtrr(pcf, smm_base, smm_size, MTRR_TYPE_WRBACK);
/* Cache the TSEG region */
postcar_enable_tseg_cache(pcf);
}
#endif