pcengines/apu1: Switch away from AGESA_LEGACY
Change-Id: I4bc357b202e6fc769dd4964a4bb774897e9fd20b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18709 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
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@ -18,7 +18,6 @@ if BOARD_PCENGINES_APU1
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config BOARD_SPECIFIC_OPTIONS # dummy
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def_bool y
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select AGESA_LEGACY
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select CPU_AMD_AGESA_FAMILY14
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select NORTHBRIDGE_AMD_AGESA_FAMILY14
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select SOUTHBRIDGE_AMD_CIMX_SB800
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@ -15,100 +15,16 @@
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* GNU General Public License for more details.
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*/
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#include <stdint.h>
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#include <string.h>
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#include <device/pci_def.h>
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#include <device/pci_ids.h>
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#include <arch/acpi.h>
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#include <arch/io.h>
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#include <arch/stages.h>
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#include <device/pnp_def.h>
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#include <arch/cpu.h>
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#include <cpu/x86/lapic.h>
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#include <console/console.h>
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#include <commonlib/loglevel.h>
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#include <cpu/x86/mtrr.h>
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#include <cpu/amd/car.h>
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#include <northbridge/amd/agesa/agesawrapper.h>
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#include <northbridge/amd/agesa/agesa_helper.h>
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#include <northbridge/amd/agesa/state_machine.h>
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#include <southbridge/amd/cimx/cimx_util.h>
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#include <cpu/x86/bist.h>
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#include <cpu/x86/cache.h>
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#include <sb_cimx.h>
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#include "SBPLATFORM.h"
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#include "cbmem.h"
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#include <cpu/amd/mtrr.h>
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#include <cpu/amd/agesa/s3_resume.h>
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#include <superio/nuvoton/common/nuvoton.h>
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#include <superio/nuvoton/nct5104d/nct5104d.h>
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#include "gpio_ftns.h"
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#include "SB800.h"
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#define SIO_PORT 0x2e
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#define SERIAL_DEV PNP_DEV(SIO_PORT, NCT5104D_SP1)
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static void early_lpc_init(void);
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void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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{
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u32 val;
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/* Must come first to enable PCI MMCONF. */
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amd_initmmio();
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if (!cpu_init_detectedx && boot_cpu()) {
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post_code(0x30);
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sb_Poweron_Init();
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early_lpc_init();
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post_code(0x31);
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nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
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console_init();
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}
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/* Halt if there was a built in self test failure */
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post_code(0x34);
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report_bist_failure(bist);
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/* Load MPB */
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val = cpuid_eax(1);
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printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
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printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
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post_code(0x37);
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agesawrapper_amdinitreset();
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post_code(0x39);
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agesawrapper_amdinitearly();
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int s3resume = acpi_is_wakeup_s3();
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if (!s3resume) {
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post_code(0x40);
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agesawrapper_amdinitpost();
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post_code(0x42);
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agesawrapper_amdinitenv();
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amd_initenv();
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} else { /* S3 detect */
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printk(BIOS_INFO, "S3 detected\n");
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post_code(0x60);
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agesawrapper_amdinitresume();
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agesawrapper_amds3laterestore();
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post_code(0x61);
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prepare_for_resume();
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}
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post_code(0x50);
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copy_and_run();
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printk(BIOS_ERR, "Error: copy_and_run() returned!\n");
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post_code(0x54); /* Should never see this post code. */
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}
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static void early_lpc_init(void)
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{
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u32 mmio_base;
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@ -141,3 +57,9 @@ static void early_lpc_init(void)
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configure_gpio(mmio_base, GPIO_190, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_LOW);
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configure_gpio(mmio_base, GPIO_191, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_LOW);
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}
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void board_BeforeAgesa(struct sysinfo *cb)
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{
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early_lpc_init();
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nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
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}
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