vendorcode/intel/fsp/fsp2_0/cpx_sp: Update to FSP ww24 release and adapt soc
The previous Intel CPX-SP FSP release was ww20 release. The ww22 release fixs issues related to FSP_NV_STORAGE HOB. The end of end flow of using memory training data to generate FSP_NV_STORAGE HOB and using memory training data passed from bootloader to skip memory training, works now. This saves 8 minutes of boot time (with FSP verbose logging enabled on DeltaLake server). This release also adds UPD parameters to support IIO bifuration. The ww24 release has following updates: a. Removed a number of unnecessary UPD parameters, such as mmiolSize, mmiolBase, OemHookPostTopologyDiscovery, OemGetResourceMapUpdate. b. Added UPD parameters to support PCIe ports configuration. c. Updated IIO_UNIVERSAL_DATA HOB, each stack now has mmio base/limit fields, in addition to PCIe resource memory base/limit fields. With ww24 release, the issue with PCIe link training persists. On YV3 config A, the onboard NIC card has x4 connection to port 2D. This NIC device is not recognized by FSP. Corresponding soc/intel/xeon_sp/cpx change is made: * There are changes in PLATFORM_DATA structure, so hob_display.c is updated. * There are changes in UPD parameters, so romstage.c is updated. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: I70762b377a057d0fca7806f485cce8d479fb5baa Reviewed-on: https://review.coreboot.org/c/coreboot/+/41903 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
parent
373ae2e734
commit
3f2f5edfed
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@ -97,14 +97,14 @@ void soc_display_iio_universal_data_hob(void)
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printk(BIOS_DEBUG, "\t===================== PLATFORM DATA =====================\n");
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printk(BIOS_DEBUG, "\tPlatGlobalIoBase: 0x%x\n", hob->PlatformData.PlatGlobalIoBase);
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printk(BIOS_DEBUG, "\tPlatGlobalIoLimit: 0x%x\n", hob->PlatformData.PlatGlobalIoLimit);
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printk(BIOS_DEBUG, "\tPlatGlobalMmiolBase: 0x%x\n",
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hob->PlatformData.PlatGlobalMmiolBase);
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printk(BIOS_DEBUG, "\tPlatGlobalMmiolLimit: 0x%x\n",
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hob->PlatformData.PlatGlobalMmiolLimit);
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printk(BIOS_DEBUG, "\tPlatGlobalMmiohBase: 0x%llx\n",
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hob->PlatformData.PlatGlobalMmiohBase);
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printk(BIOS_DEBUG, "\tPlatGlobalMmiohLimit: 0x%llx\n",
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hob->PlatformData.PlatGlobalMmiohLimit);
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printk(BIOS_DEBUG, "\tPlatGlobalMmio32Base: 0x%x\n",
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hob->PlatformData.PlatGlobalMmio32Base);
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printk(BIOS_DEBUG, "\tPlatGlobalMmio32Limit: 0x%x\n",
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hob->PlatformData.PlatGlobalMmio32Limit);
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printk(BIOS_DEBUG, "\tPlatGlobalMmio64Base: 0x%llx\n",
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hob->PlatformData.PlatGlobalMmio64Base);
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printk(BIOS_DEBUG, "\tPlatGlobalMmio64Limit: 0x%llx\n",
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hob->PlatformData.PlatGlobalMmio64Limit);
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printk(BIOS_DEBUG, "\tMemTsegSize: 0x%x\n", hob->PlatformData.MemTsegSize);
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printk(BIOS_DEBUG, "\tMemIedSize: 0x%x\n", hob->PlatformData.MemIedSize);
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printk(BIOS_DEBUG, "\tPciExpressBase: 0x%llx\n", hob->PlatformData.PciExpressBase);
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@ -33,7 +33,6 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
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/* Bitmask for valid sockets supported by the board */
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m_cfg->BoardTypeBitmask = 0x11111111;
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m_cfg->mmiolSize = 0x0;
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m_cfg->mmiohBase = 0x2000;
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/* default: 0x1 (enable), set to 0x2 (auto) */
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@ -65,9 +64,6 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
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/* the wait time in units of 1000us for PBSP to check in */
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m_cfg->WaitTimeForPSBP = 0x7530;
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m_cfg->OemHookPostTopologyDiscovery = 0xFFF7727B;
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m_cfg->OemGetResourceMapUpdate = 0xFFF7727C;
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/* Needed to avoid FSP-M reset. The default value of 0x01 is for MinPlatform */
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m_cfg->PchAdrEn = 0x02;
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@ -355,183 +355,285 @@ typedef struct {
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**/
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UINT8 UnusedUpdSpace0;
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/** Offset 0x0094 - MMIO Low Base Address
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Select MMIO Low Base Address
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0:, 1:, 2:, 3:, 4:, 5:, 6:
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**/
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UINT32 mmiolBase;
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/** Offset 0x0098 - MMIO Low Size
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Select MMIO Low Size
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$EN_DIS
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**/
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UINT32 mmiolSize;
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/** Offset 0x009C - MMIO High Base Address
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Select MMIO High Base Address
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0:, 1:, 2:, 3:, 4:, 5:, 6:
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/** Offset 0x0094 - MMIO High Base Address
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MMIO High Base Address, a hex number for Bit[51:32]
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**/
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UINT32 mmiohBase;
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/** Offset 0x00A0 - High Gap
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/** Offset 0x0098 - High Gap
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Enable or Disable High Gap
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$EN_DIS
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**/
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UINT8 highGap;
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/** Offset 0x00A1
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/** Offset 0x0099
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**/
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UINT8 UnusedUpdSpace1;
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/** Offset 0x00A2 - MMIO High Size
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Select MMIO High Size
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0:, 1:, 2:, 3:, 4:, 5:, 6:
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/** Offset 0x009A - MMIO High Size
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MMIO High Size, Number of 1GB contiguous regions to be assigned for MMIOH space
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per CPU. Range 1-1024
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**/
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UINT16 mmiohSize;
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/** Offset 0x00A4 - } TYPE:{Combo
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/** Offset 0x009C - } TYPE:{Combo
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Enable or Disable
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$EN_DIS
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**/
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UINT8 isocEn;
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/** Offset 0x00A5 - DCA
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/** Offset 0x009D - DCA
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Enable or Disable DCA
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$EN_DIS
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**/
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UINT8 dcaEn;
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/** Offset 0x00A6
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/** Offset 0x009E
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**/
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UINT8 UnusedUpdSpace2[2];
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/** Offset 0x00A8 - } TYPE:{Combo
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/** Offset 0x00A0 - } TYPE:{Combo
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Enable or Disable
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$EN_DIS
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**/
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UINT32 BoardTypeBitmask;
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/** Offset 0x00AC - } TYPE:{Combo
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/** Offset 0x00A4 - } TYPE:{Combo
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Enable or Disable
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$EN_DIS
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**/
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UINT32 AllLanesPtr;
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/** Offset 0x00B0 - } TYPE:{Combo
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/** Offset 0x00A8 - } TYPE:{Combo
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Enable or Disable
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$EN_DIS
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**/
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UINT32 PerLanePtr;
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/** Offset 0x00B4 - } TYPE:{Combo
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/** Offset 0x00AC - } TYPE:{Combo
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Enable or Disable
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$EN_DIS
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**/
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UINT32 AllLanesSizeOfTable;
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/** Offset 0x00B8 - } TYPE:{Combo
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/** Offset 0x00B0 - } TYPE:{Combo
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Enable or Disable
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$EN_DIS
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**/
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UINT32 PerLaneSizeOfTable;
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/** Offset 0x00BC - } TYPE:{Combo
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/** Offset 0x00B4 - } TYPE:{Combo
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Enable or Disable
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$EN_DIS
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**/
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UINT32 WaitTimeForPSBP;
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/** Offset 0x00C0 - } TYPE:{Combo
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/** Offset 0x00B8 - } TYPE:{Combo
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Enable or Disable
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$EN_DIS
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**/
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UINT8 IsKtiNvramDataReady;
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/** Offset 0x00C1
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**/
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UINT8 UnusedUpdSpace3[3];
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/** Offset 0x00C4 - } TYPE:{Combo
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Enable or Disable
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$EN_DIS
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**/
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UINT32 OemHookPostTopologyDiscovery;
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/** Offset 0x00C8 - } TYPE:{Combo
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Enable or Disable
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$EN_DIS
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**/
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UINT32 OemGetResourceMapUpdate;
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/** Offset 0x00CC - } TYPE:{Combo
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/** Offset 0x00B9 - } TYPE:{Combo
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Enable or Disable
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$EN_DIS
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**/
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UINT8 BoardId;
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/** Offset 0x00CD - } TYPE:{Combo
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/** Offset 0x00BA - } TYPE:{Combo
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Enable or Disable
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$EN_DIS
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**/
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UINT8 WaSerializationEn;
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/** Offset 0x00CE - } TYPE:{Combo
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/** Offset 0x00BB - } TYPE:{Combo
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Enable or Disable
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$EN_DIS
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**/
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UINT8 KtiInEnableMktme;
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/** Offset 0x00CF
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**/
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UINT8 UnusedUpdSpace4;
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/** Offset 0x00D0 - Address of IIoBifurcationTable.
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The address of the table of IIoBifurcation.
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/** Offset 0x00BC - IIO ConfigIOU0
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ConfigIOU[MAX_SOCKET][0]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4,
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0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO
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$EN_DIS
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**/
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UINT32 IIoBifurcationTablePtr;
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UINT8 IioConfigIOU0[8];
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/** Offset 0x00D4 - Number of IIoBifurcationTable Entry
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Number of IIoBifurcationTable Entry. If this is not zero, the IIoBifurcationTablePtr
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must not be NULL.
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/** Offset 0x00C4 - IIO ConfigIOU1
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ConfigIOU[MAX_SOCKET][1]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4,
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0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO
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**/
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UINT8 NumOfIIoBifurcationTable;
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UINT8 IioConfigIOU1[8];
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/** Offset 0x00D5 - PchAdrEn
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/** Offset 0x00CC - IIO ConfigIOU2
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ConfigIOU[MAX_SOCKET][2]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4,
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0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO
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**/
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UINT8 IioConfigIOU2[8];
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/** Offset 0x00D4 - IIO ConfigIOU3
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ConfigIOU[MAX_SOCKET][3]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4,
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0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO
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**/
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UINT8 IioConfigIOU3[8];
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/** Offset 0x00DC - IIO ConfigIOU4
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ConfigIOU[MAX_SOCKET][4]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4,
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0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO
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**/
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UINT8 IioConfigIOU4[8];
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/** Offset 0x00E4 - Usage type for IIO PCIE Config Table Ptr
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IIO PCIE Config Table Ptr
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**/
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UINT32 IioPcieConfigTablePtr;
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/** Offset 0x00E8 - Usage type for IIO PCIE Config Table Number
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IIO PCIE Config Table Number
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**/
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UINT32 IioPcieConfigTableNumber;
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/** Offset 0x00EC - Usage type for IIO PCIE Root Port Enable or Disable
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IIO PCH rootport, if port is enabled, the value is 0x01, if the port is disabled,
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the value is 0x00
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**/
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UINT8 IIOPcieRootPortEnable;
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/** Offset 0x00ED - Usage type for IIO DeEmphasis
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IIO DeEmphasis
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**/
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UINT8 DeEmphasis;
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/** Offset 0x00EE - Usage type for IIO PCIE Root Port link speed
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IIO root port link speed
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**/
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UINT8 IIOPciePortLinkSpeed;
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/** Offset 0x00EF - Usage type for IIO PCIE Root Port Max Payload
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IIO Root Port Max Payload
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**/
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UINT8 IIOPcieMaxPayload;
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/** Offset 0x00F0 - Usage type for IIO DfxDnTxPreset
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IIO DfxDnTxPreset
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**/
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UINT8 DfxDnTxPreset;
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/** Offset 0x00F1 - Usage type for IIO DfxRxPreset
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IIO DfxRxPreset
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**/
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UINT8 DfxRxPreset;
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/** Offset 0x00F2 - Usage type for IIO DfxUpTxPreset
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IIO DfxUpTxPreset
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**/
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UINT8 DfxUpTxPreset;
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/** Offset 0x00F3 - Usage type for IIO PcieCommonClock
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IIO PcieCommonClock
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**/
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UINT8 PcieCommonClock;
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/** Offset 0x00F4 - Usage type for IIO NtbPpd
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IIO NtbPpd
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**/
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UINT8 NtbPpd;
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/** Offset 0x00F5 - Usage type for IIO NtbBarSizeOverride
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IIO NtbBarSizeOverride
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**/
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UINT8 NtbBarSizeOverride;
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/** Offset 0x00F6 - Usage type for IIO NtbSplitBar
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IIO NtbSplitBar
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**/
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UINT8 NtbSplitBar;
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/** Offset 0x00F7 - Usage type for IIO NtbBarSizeImBar1
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IIO NtbBarSizeImBar1
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**/
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UINT8 NtbBarSizeImBar1;
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/** Offset 0x00F8 - Usage type for IIO NtbBarSizeImBar2
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IIO PNtbBarSizeImBar2
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**/
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UINT8 NtbBarSizeImBar2;
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/** Offset 0x00F9 - Usage type for IIO NtbBarSizeImBar2_0
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IIO PNtbBarSizeImBar2_0
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**/
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UINT8 NtbBarSizeImBar2_0;
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/** Offset 0x00FA - Usage type for IIO NtbBarSizeImBar2_1
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IIO NtbBarSizeImBar2_1
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**/
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UINT8 NtbBarSizeImBar2_1;
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/** Offset 0x00FB - Usage type for IIO NtbBarSizeEmBarSZ1
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IIO NtbBarSizeEmBarSZ1
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**/
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UINT8 NtbBarSizeEmBarSZ1;
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/** Offset 0x00FC - Usage type for IIO NtbBarSizeEmBarSZ2
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IIO NtbBarSizeEmBarSZ2
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**/
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UINT8 NtbBarSizeEmBarSZ2;
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/** Offset 0x00FD - Usage type for IIO NtbBarSizeEmBarSZ2_0
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IIO NtbBarSizeEmBarSZ2_0
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**/
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UINT8 NtbBarSizeEmBarSZ2_0;
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/** Offset 0x00FE - Usage type for IIO NtbBarSizeEmBarSZ2_1
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IIO NtbBarSizeEmBarSZ2_1
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**/
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UINT8 NtbBarSizeEmBarSZ2_1;
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/** Offset 0x00FF - Usage type for IIO NtbXlinkCtlOverride
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IIO NtbXlinkCtlOverride
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**/
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UINT8 NtbXlinkCtlOverride;
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/** Offset 0x0100 - PchAdrEn
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Enable or Disable PchSirqMode
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**/
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UINT8 PchSirqMode;
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/** Offset 0x0101 - PchAdrEn
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Enable or Disable PchAdr
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**/
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UINT8 PchAdrEn;
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/** Offset 0x00D6 - } TYPE:{Combo
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Enable or Disable
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$EN_DIS
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/** Offset 0x0102 - } TYPE:{Combo
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Root port swapping based on device connection status : TRUE or FALSE
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TRUE : 0x01, FALSE : 0x00
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**/
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UINT8 PchPcieRootPortFunctionSwap;
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/** Offset 0x00D7 - PCH PCIE PLL Ssc
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/** Offset 0x0103 - PCH PCIE PLL Ssc
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Valid spread range : 0x00-0x14 (A value of 0 is SSC of 0.0%. A value of 20 is SSC
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of 2.0%), Auto : 0xFE(Set to hardware default), Disable : 0xFF
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**/
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UINT8 PchPciePllSsc;
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/** Offset 0x00D8 - Usage type for PCH PCIE Root Port Index
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/** Offset 0x0104 - Usage type for PCH PCIE Root Port Index
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Index assigned to every PCH PCIE Root Port
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**/
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UINT8 PchPciePortIndex[20];
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/** Offset 0x00EC - Usage type for PCH PCIE Root Port Enable or Disable
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0-19: PCH rootport, 0x40-0x43: PEG port, 0x70:LAN, 0x80: unspecified but in use
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(free running), 0xFF: not used
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/** Offset 0x0118 - Usage type for PCH PCIE Root Port Enable or Disable
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0-19: PCH rootport, if port is enabled, the value is 0x01, if the port is disabled,
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the value is 0x00
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**/
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UINT8 PchPcieForceEnable[20];
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/** Offset 0x0100 - Usage type for PCH PCIE Root Port Link Speed
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0-19: PCH rootport, 0x40-0x43: PEG port, 0x70:LAN, 0x80: unspecified but in use
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(free running), 0xFF: not used
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/** Offset 0x012C - Usage type for PCH PCIE Root Port Link Speed
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0-19: PCH rootport, 0x00 : Pcie Auto Speed, 0x01 : Pcie Gen1 Speed, 0x02 : Pcie
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Gen2 Speed, 0x03 : Pcie Gen3 Speed
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**/
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UINT8 PchPciePortLinkSpeed[20];
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/** Offset 0x0114
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/** Offset 0x0140
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**/
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UINT8 ReservedMemoryInitUpd[16];
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} FSP_M_CONFIG;
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@ -552,11 +654,11 @@ typedef struct {
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**/
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FSP_M_CONFIG FspmConfig;
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/** Offset 0x0124
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/** Offset 0x0150
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**/
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UINT8 UnusedUpdSpace5[2];
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UINT8 UnusedUpdSpace3[6];
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/** Offset 0x0126
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/** Offset 0x0156
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**/
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UINT16 UpdTerminator;
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} FSPM_UPD;
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@ -203,6 +203,10 @@ typedef struct _STACK_RES {
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uint16_t PciResourceIoLimit;
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uint32_t IoApicBase;
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uint32_t IoApicLimit;
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uint32_t Mmio32Base;
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uint32_t Mmio32Limit;
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uint64_t Mmio64Base;
|
||||
uint64_t Mmio64Limit;
|
||||
uint32_t PciResourceMem32Base;
|
||||
uint32_t PciResourceMem32Limit;
|
||||
uint64_t PciResourceMem64Base;
|
||||
|
@ -233,10 +237,10 @@ typedef struct {
|
|||
typedef struct {
|
||||
uint16_t PlatGlobalIoBase; // Global IO Base
|
||||
uint16_t PlatGlobalIoLimit; // Global IO Limit
|
||||
uint32_t PlatGlobalMmiolBase; // Global Mmiol base
|
||||
uint32_t PlatGlobalMmiolLimit; // Global Mmiol limit
|
||||
uint64_t PlatGlobalMmiohBase; // Global Mmioh Base [43:0]
|
||||
uint64_t PlatGlobalMmiohLimit; // Global Mmioh Limit [43:0]
|
||||
uint32_t PlatGlobalMmio32Base; // Global Mmiol base
|
||||
uint32_t PlatGlobalMmio32Limit; // Global Mmiol limit
|
||||
uint64_t PlatGlobalMmio64Base; // Global Mmioh Base [43:0]
|
||||
uint64_t PlatGlobalMmio64Limit; // Global Mmioh Limit [43:0]
|
||||
QPI_CPU_DATA CpuQpiInfo[MAX_SOCKET]; // QPI related info per CPU
|
||||
QPI_IIO_DATA IioQpiInfo[MAX_SOCKET]; // QPI related info per IIO
|
||||
uint32_t MemTsegSize;
|
||||
|
@ -256,10 +260,8 @@ typedef struct {
|
|||
uint32_t MmiolGranularity;
|
||||
UINT64_STRUCT MmiohGranularity;
|
||||
uint8_t RemoteRequestThreshold; //5370389
|
||||
uint64_t softskuSocketPresentBitMap; // bitmap of Softsku sockets with CPUs present detected
|
||||
uint32_t UboxMmioSize;
|
||||
uint32_t MaxAddressBits;
|
||||
uint32_t DmiReservedMmiolSize[MAX_SOCKET];
|
||||
} PLATFORM_DATA;
|
||||
|
||||
typedef struct {
|
||||
|
@ -273,7 +275,6 @@ typedef struct {
|
|||
uint8_t DmiVc1;
|
||||
uint8_t DmiVcm;
|
||||
uint32_t CpuPCPSInfo;
|
||||
uint8_t LtsxEnable;
|
||||
uint8_t MctpEn;
|
||||
uint8_t cpuSubType;
|
||||
uint8_t SystemRasType;
|
||||
|
|
|
@ -99,7 +99,12 @@ typedef struct SystemMemoryMapHob {
|
|||
UINT8 numberEntries; // Number of Memory Map Elements
|
||||
SYSTEM_MEMORY_MAP_ELEMENT Element[MAX_SOCKET * MAX_DRAM_CLUSTERS * MAX_SAD_RULES];
|
||||
|
||||
UINT8 reserved3[24409];
|
||||
UINT8 reserved3[24417];
|
||||
|
||||
UINT32 MmiohBase; // MMIOH base in 64MB granularity
|
||||
|
||||
UINT8 reserved4[10];
|
||||
|
||||
} SYSTEM_MEMORY_MAP_HOB;
|
||||
|
||||
#pragma pack()
|
||||
|
|
Loading…
Reference in New Issue