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vendorcode/intel/fsp/fsp2_0/cpx_sp: Update to FSP ww24 release and adapt soc 

The previous Intel CPX-SP FSP release was ww20 release.

The ww22 release fixs issues related to FSP_NV_STORAGE HOB. The end of end
flow of using memory training data to generate FSP_NV_STORAGE HOB and
using memory training data passed from bootloader to skip memory
training, works now. This saves 8 minutes of boot time (with FSP verbose
logging enabled on DeltaLake server).

This release also adds UPD parameters to support IIO bifuration.

The ww24 release has following updates:
a. Removed a number of unnecessary UPD parameters, such as mmiolSize,
mmiolBase, OemHookPostTopologyDiscovery, OemGetResourceMapUpdate.
b. Added UPD parameters to support PCIe ports configuration.
c. Updated IIO_UNIVERSAL_DATA HOB, each stack now has mmio base/limit
fields, in addition to PCIe resource memory base/limit fields.

With ww24 release, the issue with PCIe link training persists. On YV3
config A, the onboard NIC card has x4 connection to port 2D. This
NIC device is not recognized by FSP.

Corresponding soc/intel/xeon_sp/cpx change is made:
* There are changes in PLATFORM_DATA structure, so hob_display.c
is updated.
* There are changes in UPD parameters, so romstage.c is updated.

Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: I70762b377a057d0fca7806f485cce8d479fb5baa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41903
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Jonathan Zhang 2020-05-29 11:57:55 -07:00 committed by Patrick Georgi
parent 373ae2e734
commit 3f2f5edfed
5 changed files with 200 additions and 96 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
src/soc/intel/xeon_sp/cpx/hob_display.c
View File

@ -97,14 +97,14 @@ void soc_display_iio_universal_data_hob(void)
printk(BIOS_DEBUG, "\t===================== PLATFORM DATA =====================\n"); printk(BIOS_DEBUG, "\t===================== PLATFORM DATA =====================\n");
printk(BIOS_DEBUG, "\tPlatGlobalIoBase: 0x%x\n", hob->PlatformData.PlatGlobalIoBase); printk(BIOS_DEBUG, "\tPlatGlobalIoBase: 0x%x\n", hob->PlatformData.PlatGlobalIoBase);
printk(BIOS_DEBUG, "\tPlatGlobalIoLimit: 0x%x\n", hob->PlatformData.PlatGlobalIoLimit); printk(BIOS_DEBUG, "\tPlatGlobalIoLimit: 0x%x\n", hob->PlatformData.PlatGlobalIoLimit);
printk(BIOS_DEBUG, "\tPlatGlobalMmiolBase: 0x%x\n", printk(BIOS_DEBUG, "\tPlatGlobalMmio32Base: 0x%x\n",
hob->PlatformData.PlatGlobalMmiolBase); hob->PlatformData.PlatGlobalMmio32Base);
printk(BIOS_DEBUG, "\tPlatGlobalMmiolLimit: 0x%x\n", printk(BIOS_DEBUG, "\tPlatGlobalMmio32Limit: 0x%x\n",
hob->PlatformData.PlatGlobalMmiolLimit); hob->PlatformData.PlatGlobalMmio32Limit);
printk(BIOS_DEBUG, "\tPlatGlobalMmiohBase: 0x%llx\n", printk(BIOS_DEBUG, "\tPlatGlobalMmio64Base: 0x%llx\n",
hob->PlatformData.PlatGlobalMmiohBase); hob->PlatformData.PlatGlobalMmio64Base);
printk(BIOS_DEBUG, "\tPlatGlobalMmiohLimit: 0x%llx\n", printk(BIOS_DEBUG, "\tPlatGlobalMmio64Limit: 0x%llx\n",
hob->PlatformData.PlatGlobalMmiohLimit); hob->PlatformData.PlatGlobalMmio64Limit);
printk(BIOS_DEBUG, "\tMemTsegSize: 0x%x\n", hob->PlatformData.MemTsegSize); printk(BIOS_DEBUG, "\tMemTsegSize: 0x%x\n", hob->PlatformData.MemTsegSize);
printk(BIOS_DEBUG, "\tMemIedSize: 0x%x\n", hob->PlatformData.MemIedSize); printk(BIOS_DEBUG, "\tMemIedSize: 0x%x\n", hob->PlatformData.MemIedSize);
printk(BIOS_DEBUG, "\tPciExpressBase: 0x%llx\n", hob->PlatformData.PciExpressBase); printk(BIOS_DEBUG, "\tPciExpressBase: 0x%llx\n", hob->PlatformData.PciExpressBase);

4
src/soc/intel/xeon_sp/cpx/romstage.c
View File

@ -33,7 +33,6 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
/* Bitmask for valid sockets supported by the board */ /* Bitmask for valid sockets supported by the board */
m_cfg->BoardTypeBitmask = 0x11111111; m_cfg->BoardTypeBitmask = 0x11111111;
m_cfg->mmiolSize = 0x0;
m_cfg->mmiohBase = 0x2000; m_cfg->mmiohBase = 0x2000;
/* default: 0x1 (enable), set to 0x2 (auto) */ /* default: 0x1 (enable), set to 0x2 (auto) */
@ -65,9 +64,6 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
/* the wait time in units of 1000us for PBSP to check in */ /* the wait time in units of 1000us for PBSP to check in */
m_cfg->WaitTimeForPSBP = 0x7530; m_cfg->WaitTimeForPSBP = 0x7530;
m_cfg->OemHookPostTopologyDiscovery = 0xFFF7727B;
m_cfg->OemGetResourceMapUpdate = 0xFFF7727C;
/* Needed to avoid FSP-M reset. The default value of 0x01 is for MinPlatform */ /* Needed to avoid FSP-M reset. The default value of 0x01 is for MinPlatform */
m_cfg->PchAdrEn = 0x02; m_cfg->PchAdrEn = 0x02;

254
src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h
View File

@ -355,183 +355,285 @@ typedef struct {
**/ **/
UINT8 UnusedUpdSpace0; UINT8 UnusedUpdSpace0;
/** Offset 0x0094 - MMIO Low Base Address /** Offset 0x0094 - MMIO High Base Address
Select MMIO Low Base Address MMIO High Base Address, a hex number for Bit[51:32]
0:, 1:, 2:, 3:, 4:, 5:, 6:
**/
UINT32 mmiolBase;
/** Offset 0x0098 - MMIO Low Size
Select MMIO Low Size
$EN_DIS
**/
UINT32 mmiolSize;
/** Offset 0x009C - MMIO High Base Address
Select MMIO High Base Address
0:, 1:, 2:, 3:, 4:, 5:, 6:
**/ **/
UINT32 mmiohBase; UINT32 mmiohBase;
/** Offset 0x00A0 - High Gap /** Offset 0x0098 - High Gap
Enable or Disable High Gap Enable or Disable High Gap
$EN_DIS $EN_DIS
**/ **/
UINT8 highGap; UINT8 highGap;
/** Offset 0x00A1 /** Offset 0x0099
**/ **/
UINT8 UnusedUpdSpace1; UINT8 UnusedUpdSpace1;
/** Offset 0x00A2 - MMIO High Size /** Offset 0x009A - MMIO High Size
Select MMIO High Size MMIO High Size, Number of 1GB contiguous regions to be assigned for MMIOH space
0:, 1:, 2:, 3:, 4:, 5:, 6: per CPU. Range 1-1024
**/ **/
UINT16 mmiohSize; UINT16 mmiohSize;
/** Offset 0x00A4 - } TYPE:{Combo /** Offset 0x009C - } TYPE:{Combo
Enable or Disable Enable or Disable
$EN_DIS $EN_DIS
**/ **/
UINT8 isocEn; UINT8 isocEn;
/** Offset 0x00A5 - DCA /** Offset 0x009D - DCA
Enable or Disable DCA Enable or Disable DCA
$EN_DIS $EN_DIS
**/ **/
UINT8 dcaEn; UINT8 dcaEn;
/** Offset 0x00A6 /** Offset 0x009E
**/ **/
UINT8 UnusedUpdSpace2[2]; UINT8 UnusedUpdSpace2[2];
/** Offset 0x00A8 - } TYPE:{Combo /** Offset 0x00A0 - } TYPE:{Combo
Enable or Disable Enable or Disable
$EN_DIS $EN_DIS
**/ **/
UINT32 BoardTypeBitmask; UINT32 BoardTypeBitmask;
/** Offset 0x00AC - } TYPE:{Combo /** Offset 0x00A4 - } TYPE:{Combo
Enable or Disable Enable or Disable
$EN_DIS $EN_DIS
**/ **/
UINT32 AllLanesPtr; UINT32 AllLanesPtr;
/** Offset 0x00B0 - } TYPE:{Combo /** Offset 0x00A8 - } TYPE:{Combo
Enable or Disable Enable or Disable
$EN_DIS $EN_DIS
**/ **/
UINT32 PerLanePtr; UINT32 PerLanePtr;
/** Offset 0x00B4 - } TYPE:{Combo /** Offset 0x00AC - } TYPE:{Combo
Enable or Disable Enable or Disable
$EN_DIS $EN_DIS
**/ **/
UINT32 AllLanesSizeOfTable; UINT32 AllLanesSizeOfTable;
/** Offset 0x00B8 - } TYPE:{Combo /** Offset 0x00B0 - } TYPE:{Combo
Enable or Disable Enable or Disable
$EN_DIS $EN_DIS
**/ **/
UINT32 PerLaneSizeOfTable; UINT32 PerLaneSizeOfTable;
/** Offset 0x00BC - } TYPE:{Combo /** Offset 0x00B4 - } TYPE:{Combo
Enable or Disable Enable or Disable
$EN_DIS $EN_DIS
**/ **/
UINT32 WaitTimeForPSBP; UINT32 WaitTimeForPSBP;
/** Offset 0x00C0 - } TYPE:{Combo /** Offset 0x00B8 - } TYPE:{Combo
Enable or Disable Enable or Disable
$EN_DIS $EN_DIS
**/ **/
UINT8 IsKtiNvramDataReady; UINT8 IsKtiNvramDataReady;
/** Offset 0x00C1 /** Offset 0x00B9 - } TYPE:{Combo
**/
UINT8 UnusedUpdSpace3[3];
/** Offset 0x00C4 - } TYPE:{Combo
Enable or Disable
$EN_DIS
**/
UINT32 OemHookPostTopologyDiscovery;
/** Offset 0x00C8 - } TYPE:{Combo
Enable or Disable
$EN_DIS
**/
UINT32 OemGetResourceMapUpdate;
/** Offset 0x00CC - } TYPE:{Combo
Enable or Disable Enable or Disable
$EN_DIS $EN_DIS
**/ **/
UINT8 BoardId; UINT8 BoardId;
/** Offset 0x00CD - } TYPE:{Combo /** Offset 0x00BA - } TYPE:{Combo
Enable or Disable Enable or Disable
$EN_DIS $EN_DIS
**/ **/
UINT8 WaSerializationEn; UINT8 WaSerializationEn;
/** Offset 0x00CE - } TYPE:{Combo /** Offset 0x00BB - } TYPE:{Combo
Enable or Disable Enable or Disable
$EN_DIS $EN_DIS
**/ **/
UINT8 KtiInEnableMktme; UINT8 KtiInEnableMktme;
/** Offset 0x00CF /** Offset 0x00BC - IIO ConfigIOU0
**/ ConfigIOU[MAX_SOCKET][0]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4,
UINT8 UnusedUpdSpace4; 0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO
/** Offset 0x00D0 - Address of IIoBifurcationTable.
The address of the table of IIoBifurcation.
$EN_DIS $EN_DIS
**/ **/
UINT32 IIoBifurcationTablePtr; UINT8 IioConfigIOU0[8];
/** Offset 0x00D4 - Number of IIoBifurcationTable Entry /** Offset 0x00C4 - IIO ConfigIOU1
Number of IIoBifurcationTable Entry. If this is not zero, the IIoBifurcationTablePtr ConfigIOU[MAX_SOCKET][1]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4,
must not be NULL. 0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO
**/ **/
UINT8 NumOfIIoBifurcationTable; UINT8 IioConfigIOU1[8];
/** Offset 0x00D5 - PchAdrEn /** Offset 0x00CC - IIO ConfigIOU2
ConfigIOU[MAX_SOCKET][2]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4,
0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO
**/
UINT8 IioConfigIOU2[8];
/** Offset 0x00D4 - IIO ConfigIOU3
ConfigIOU[MAX_SOCKET][3]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4,
0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO
**/
UINT8 IioConfigIOU3[8];
/** Offset 0x00DC - IIO ConfigIOU4
ConfigIOU[MAX_SOCKET][4]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4,
0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO
**/
UINT8 IioConfigIOU4[8];
/** Offset 0x00E4 - Usage type for IIO PCIE Config Table Ptr
IIO PCIE Config Table Ptr
**/
UINT32 IioPcieConfigTablePtr;
/** Offset 0x00E8 - Usage type for IIO PCIE Config Table Number
IIO PCIE Config Table Number
**/
UINT32 IioPcieConfigTableNumber;
/** Offset 0x00EC - Usage type for IIO PCIE Root Port Enable or Disable
IIO PCH rootport, if port is enabled, the value is 0x01, if the port is disabled,
the value is 0x00
**/
UINT8 IIOPcieRootPortEnable;
/** Offset 0x00ED - Usage type for IIO DeEmphasis
IIO DeEmphasis
**/
UINT8 DeEmphasis;
/** Offset 0x00EE - Usage type for IIO PCIE Root Port link speed
IIO root port link speed
**/
UINT8 IIOPciePortLinkSpeed;
/** Offset 0x00EF - Usage type for IIO PCIE Root Port Max Payload
IIO Root Port Max Payload
**/
UINT8 IIOPcieMaxPayload;
/** Offset 0x00F0 - Usage type for IIO DfxDnTxPreset
IIO DfxDnTxPreset
**/
UINT8 DfxDnTxPreset;
/** Offset 0x00F1 - Usage type for IIO DfxRxPreset
IIO DfxRxPreset
**/
UINT8 DfxRxPreset;
/** Offset 0x00F2 - Usage type for IIO DfxUpTxPreset
IIO DfxUpTxPreset
**/
UINT8 DfxUpTxPreset;
/** Offset 0x00F3 - Usage type for IIO PcieCommonClock
IIO PcieCommonClock
**/
UINT8 PcieCommonClock;
/** Offset 0x00F4 - Usage type for IIO NtbPpd
IIO NtbPpd
**/
UINT8 NtbPpd;
/** Offset 0x00F5 - Usage type for IIO NtbBarSizeOverride
IIO NtbBarSizeOverride
**/
UINT8 NtbBarSizeOverride;
/** Offset 0x00F6 - Usage type for IIO NtbSplitBar
IIO NtbSplitBar
**/
UINT8 NtbSplitBar;
/** Offset 0x00F7 - Usage type for IIO NtbBarSizeImBar1
IIO NtbBarSizeImBar1
**/
UINT8 NtbBarSizeImBar1;
/** Offset 0x00F8 - Usage type for IIO NtbBarSizeImBar2
IIO PNtbBarSizeImBar2
**/
UINT8 NtbBarSizeImBar2;
/** Offset 0x00F9 - Usage type for IIO NtbBarSizeImBar2_0
IIO PNtbBarSizeImBar2_0
**/
UINT8 NtbBarSizeImBar2_0;
/** Offset 0x00FA - Usage type for IIO NtbBarSizeImBar2_1
IIO NtbBarSizeImBar2_1
**/
UINT8 NtbBarSizeImBar2_1;
/** Offset 0x00FB - Usage type for IIO NtbBarSizeEmBarSZ1
IIO NtbBarSizeEmBarSZ1
**/
UINT8 NtbBarSizeEmBarSZ1;
/** Offset 0x00FC - Usage type for IIO NtbBarSizeEmBarSZ2
IIO NtbBarSizeEmBarSZ2
**/
UINT8 NtbBarSizeEmBarSZ2;
/** Offset 0x00FD - Usage type for IIO NtbBarSizeEmBarSZ2_0
IIO NtbBarSizeEmBarSZ2_0
**/
UINT8 NtbBarSizeEmBarSZ2_0;
/** Offset 0x00FE - Usage type for IIO NtbBarSizeEmBarSZ2_1
IIO NtbBarSizeEmBarSZ2_1
**/
UINT8 NtbBarSizeEmBarSZ2_1;
/** Offset 0x00FF - Usage type for IIO NtbXlinkCtlOverride
IIO NtbXlinkCtlOverride
**/
UINT8 NtbXlinkCtlOverride;
/** Offset 0x0100 - PchAdrEn
Enable or Disable PchSirqMode
**/
UINT8 PchSirqMode;
/** Offset 0x0101 - PchAdrEn
Enable or Disable PchAdr Enable or Disable PchAdr
**/ **/
UINT8 PchAdrEn; UINT8 PchAdrEn;
/** Offset 0x00D6 - } TYPE:{Combo /** Offset 0x0102 - } TYPE:{Combo
Enable or Disable Root port swapping based on device connection status : TRUE or FALSE
$EN_DIS TRUE : 0x01, FALSE : 0x00
**/ **/
UINT8 PchPcieRootPortFunctionSwap; UINT8 PchPcieRootPortFunctionSwap;
/** Offset 0x00D7 - PCH PCIE PLL Ssc /** Offset 0x0103 - PCH PCIE PLL Ssc
Valid spread range : 0x00-0x14 (A value of 0 is SSC of 0.0%. A value of 20 is SSC Valid spread range : 0x00-0x14 (A value of 0 is SSC of 0.0%. A value of 20 is SSC
of 2.0%), Auto : 0xFE(Set to hardware default), Disable : 0xFF of 2.0%), Auto : 0xFE(Set to hardware default), Disable : 0xFF
**/ **/
UINT8 PchPciePllSsc; UINT8 PchPciePllSsc;
/** Offset 0x00D8 - Usage type for PCH PCIE Root Port Index /** Offset 0x0104 - Usage type for PCH PCIE Root Port Index
Index assigned to every PCH PCIE Root Port Index assigned to every PCH PCIE Root Port
**/ **/
UINT8 PchPciePortIndex[20]; UINT8 PchPciePortIndex[20];
/** Offset 0x00EC - Usage type for PCH PCIE Root Port Enable or Disable /** Offset 0x0118 - Usage type for PCH PCIE Root Port Enable or Disable
0-19: PCH rootport, 0x40-0x43: PEG port, 0x70:LAN, 0x80: unspecified but in use 0-19: PCH rootport, if port is enabled, the value is 0x01, if the port is disabled,
(free running), 0xFF: not used the value is 0x00
**/ **/
UINT8 PchPcieForceEnable[20]; UINT8 PchPcieForceEnable[20];
/** Offset 0x0100 - Usage type for PCH PCIE Root Port Link Speed /** Offset 0x012C - Usage type for PCH PCIE Root Port Link Speed
0-19: PCH rootport, 0x40-0x43: PEG port, 0x70:LAN, 0x80: unspecified but in use 0-19: PCH rootport, 0x00 : Pcie Auto Speed, 0x01 : Pcie Gen1 Speed, 0x02 : Pcie
(free running), 0xFF: not used Gen2 Speed, 0x03 : Pcie Gen3 Speed
**/ **/
UINT8 PchPciePortLinkSpeed[20]; UINT8 PchPciePortLinkSpeed[20];
/** Offset 0x0114 /** Offset 0x0140
**/ **/
UINT8 ReservedMemoryInitUpd[16]; UINT8 ReservedMemoryInitUpd[16];
} FSP_M_CONFIG; } FSP_M_CONFIG;
@ -552,11 +654,11 @@ typedef struct {
**/ **/
FSP_M_CONFIG FspmConfig; FSP_M_CONFIG FspmConfig;
/** Offset 0x0124 /** Offset 0x0150
**/ **/
UINT8 UnusedUpdSpace5[2]; UINT8 UnusedUpdSpace3[6];
/** Offset 0x0126 /** Offset 0x0156
**/ **/
UINT16 UpdTerminator; UINT16 UpdTerminator;
} FSPM_UPD; } FSPM_UPD;

15
src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h
View File

@ -203,6 +203,10 @@ typedef struct _STACK_RES {
uint16_t PciResourceIoLimit; uint16_t PciResourceIoLimit;
uint32_t IoApicBase; uint32_t IoApicBase;
uint32_t IoApicLimit; uint32_t IoApicLimit;
uint32_t Mmio32Base;
uint32_t Mmio32Limit;
uint64_t Mmio64Base;
uint64_t Mmio64Limit;
uint32_t PciResourceMem32Base; uint32_t PciResourceMem32Base;
uint32_t PciResourceMem32Limit; uint32_t PciResourceMem32Limit;
uint64_t PciResourceMem64Base; uint64_t PciResourceMem64Base;
@ -233,10 +237,10 @@ typedef struct {
typedef struct { typedef struct {
uint16_t PlatGlobalIoBase; // Global IO Base uint16_t PlatGlobalIoBase; // Global IO Base
uint16_t PlatGlobalIoLimit; // Global IO Limit uint16_t PlatGlobalIoLimit; // Global IO Limit
uint32_t PlatGlobalMmiolBase; // Global Mmiol base uint32_t PlatGlobalMmio32Base; // Global Mmiol base
uint32_t PlatGlobalMmiolLimit; // Global Mmiol limit uint32_t PlatGlobalMmio32Limit; // Global Mmiol limit
uint64_t PlatGlobalMmiohBase; // Global Mmioh Base [43:0] uint64_t PlatGlobalMmio64Base; // Global Mmioh Base [43:0]
uint64_t PlatGlobalMmiohLimit; // Global Mmioh Limit [43:0] uint64_t PlatGlobalMmio64Limit; // Global Mmioh Limit [43:0]
QPI_CPU_DATA CpuQpiInfo[MAX_SOCKET]; // QPI related info per CPU QPI_CPU_DATA CpuQpiInfo[MAX_SOCKET]; // QPI related info per CPU
QPI_IIO_DATA IioQpiInfo[MAX_SOCKET]; // QPI related info per IIO QPI_IIO_DATA IioQpiInfo[MAX_SOCKET]; // QPI related info per IIO
uint32_t MemTsegSize; uint32_t MemTsegSize;
@ -256,10 +260,8 @@ typedef struct {
uint32_t MmiolGranularity; uint32_t MmiolGranularity;
UINT64_STRUCT MmiohGranularity; UINT64_STRUCT MmiohGranularity;
uint8_t RemoteRequestThreshold; //5370389 uint8_t RemoteRequestThreshold; //5370389
uint64_t softskuSocketPresentBitMap; // bitmap of Softsku sockets with CPUs present detected
uint32_t UboxMmioSize; uint32_t UboxMmioSize;
uint32_t MaxAddressBits; uint32_t MaxAddressBits;
uint32_t DmiReservedMmiolSize[MAX_SOCKET];
} PLATFORM_DATA; } PLATFORM_DATA;
typedef struct { typedef struct {
@ -273,7 +275,6 @@ typedef struct {
uint8_t DmiVc1; uint8_t DmiVc1;
uint8_t DmiVcm; uint8_t DmiVcm;
uint32_t CpuPCPSInfo; uint32_t CpuPCPSInfo;
uint8_t LtsxEnable;
uint8_t MctpEn; uint8_t MctpEn;
uint8_t cpuSubType; uint8_t cpuSubType;
uint8_t SystemRasType; uint8_t SystemRasType;

7
src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h
View File

@ -99,7 +99,12 @@ typedef struct SystemMemoryMapHob {
UINT8 numberEntries; // Number of Memory Map Elements UINT8 numberEntries; // Number of Memory Map Elements
SYSTEM_MEMORY_MAP_ELEMENT Element[MAX_SOCKET * MAX_DRAM_CLUSTERS * MAX_SAD_RULES]; SYSTEM_MEMORY_MAP_ELEMENT Element[MAX_SOCKET * MAX_DRAM_CLUSTERS * MAX_SAD_RULES];
UINT8 reserved3[24409]; UINT8 reserved3[24417];
UINT32 MmiohBase; // MMIOH base in 64MB granularity
UINT8 reserved4[10];
} SYSTEM_MEMORY_MAP_HOB; } SYSTEM_MEMORY_MAP_HOB;
#pragma pack() #pragma pack()