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southbridge/intel/lynxpoint: Fix undefined behavior 

Fix undefined behavior found by clang's -Wshift-sign-overflow, grep,
and source inspection. Left shifting an int where the right operand is
>= the width of the type is undefined. Add UL suffix since it's safe
for unsigned types.

Change-Id: I10db2566199200ceb3068721cfb35eadb2be1f68
Signed-off-by: Ryan Salsamendi <rsalsamendi@hotmail.com>
Reviewed-on: https://review.coreboot.org/20464
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Ryan Salsamendi 2017-07-04 13:14:16 -07:00 committed by Martin Roth
parent 2fdf895867
commit 3f2fe18965
6 changed files with 12 additions and 10 deletions
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4
src/southbridge/intel/lynxpoint/finalize.c
View File

@ -40,7 +40,7 @@ void intel_pch_finalize_smm(void)
#endif
/* TCLOCKDN: TC Lockdown */
RCBA32_OR(0x0050, (1 << 31));
RCBA32_OR(0x0050, (1UL << 31));
/* BIOS Interface Lockdown */
RCBA32_OR(0x3410, (1 << 0));
@ -55,7 +55,7 @@ void intel_pch_finalize_smm(void)
pci_or_config8(PCH_LPC_DEV, 0xa6, (1 << 1) | (1 << 2));
/* PMSYNC */
RCBA32_OR(PMSYNC_CONFIG, (1 << 31));
RCBA32_OR(PMSYNC_CONFIG, (1UL << 31));
/* R/WO registers */
RCBA32(0x21a4) = RCBA32(0x21a4);

6
src/southbridge/intel/lynxpoint/lp_gpio.h
View File

@ -51,9 +51,9 @@
#define GPI_LEVEL (1 << 30)
#define GPO_LEVEL_SHIFT 31
#define GPO_LEVEL_MASK (1 << GPO_LEVEL_SHIFT)
#define GPO_LEVEL_LOW (0 << GPO_LEVEL_SHIFT)
#define GPO_LEVEL_HIGH (1 << GPO_LEVEL_SHIFT)
#define GPO_LEVEL_MASK (1UL << GPO_LEVEL_SHIFT)
#define GPO_LEVEL_LOW (0UL << GPO_LEVEL_SHIFT)
#define GPO_LEVEL_HIGH (1UL << GPO_LEVEL_SHIFT)
/* conf1 */

2
src/southbridge/intel/lynxpoint/lpc.c
View File

@ -475,7 +475,7 @@ static void enable_lp_clock_gating(device_t dev)
reg32 &= ~(1 << 29); // LPC Dynamic
else
reg32 |= (1 << 29); // LPC Dynamic
reg32 |= (1 << 31); // LP LPC
reg32 |= (1UL << 31); // LP LPC
reg32 |= (1 << 30); // LP BLA
reg32 |= (1 << 28); // GPIO Dynamic
reg32 |= (1 << 27); // HPET Dynamic

4
src/southbridge/intel/lynxpoint/pch.h
View File

@ -242,7 +242,7 @@ void pch_enable_lpc(void);
#define GEN_PMCON_2 0xa2
#define GEN_PMCON_3 0xa4
#define PMIR 0xac
#define PMIR_CF9LOCK (1 << 31)
#define PMIR_CF9LOCK (1UL << 31)
#define PMIR_CF9GR (1 << 20)
/* GEN_PMCON_3 bits */
@ -389,7 +389,7 @@ void pch_enable_lpc(void);
#define XHCI_USB3_PORTSC_WRC (1 << 19) /* Warm Reset Complete */
#define XHCI_USB3_PORTSC_LWS (1 << 16) /* Link Write Strobe */
#define XHCI_USB3_PORTSC_PED (1 << 1) /* Port Enabled/Disabled */
#define XHCI_USB3_PORTSC_WPR (1 << 31) /* Warm Port Reset */
#define XHCI_USB3_PORTSC_WPR (1UL << 31) /* Warm Port Reset */
#define XHCI_USB3_PORTSC_PLS (0xf << 5) /* Port Link State */
#define XHCI_PLSR_DISABLED (4 << 5) /* Port is disabled */
#define XHCI_PLSR_RXDETECT (5 << 5) /* Port is disconnected */

4
src/southbridge/intel/lynxpoint/pcie.c
View File

@ -193,6 +193,8 @@ static void pcie_enable_clock_gating(void)
rp = root_port_number(dev);
if (!dev->enabled) {
static const uint32_t high_bit = (1UL << 31);
/* Configure shared resource clock gating. */
if (rp == 1 || rp == 5 || (rp == 6 && is_lp))
pci_update_config8(dev, 0xe1, 0xc3, 0x3c);
@ -214,7 +216,7 @@ static void pcie_enable_clock_gating(void)
}
pci_update_config8(dev, 0xe2, ~(3 << 4), (3 << 4));
pci_update_config32(dev, 0x420, ~(1 << 31), (1 << 31));
pci_update_config32(dev, 0x420, ~high_bit, high_bit);
/* Per-Port CLKREQ# handling. */
if (is_lp && gpio_is_native(18 + rp - 1))

2
src/southbridge/intel/lynxpoint/sata.c
View File

@ -134,7 +134,7 @@ static void sata_init(struct device *dev)
reg32 |= 1 << 18; /* BWG step 10 */
reg32 |= 1 << 29; /* BWG step 11 */
if (pch_is_lp()) {
reg32 &= ~((1 << 31) | (1 << 30));
reg32 &= ~((1UL << 31) | (1 << 30));
reg32 |= 1 << 23;
reg32 |= 1 << 24; /* Disable listen mode (hotplug) */
}