purism/librem_skl: Add AC/DC LoadLine to VR Config
The FSP 2.0 needs to set the ac_loadline and dc_loadline for each VR config. Without it, the Loadline is considered to be 0 mOhm and this causes CPU temp to jump all over the place whenever the CPU is used. This is necessary since there are no VR_CONFIG icc mappings for Skylake SKUs, only KabyLake. These values were copied from the Google Poppy devicetree. Change-Id: I6aeb6ee521988b94f2ae94a60d1a28b87ba984d4 Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Reviewed-on: https://review.coreboot.org/25324 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Youness Alaoui
Patrick Georgi
parent
cb8f04dc83
commit
3f42a26b42
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@ -31,8 +31,8 @@ chip soc/intel/skylake
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# Enable "Intel Speed Shift Technology"
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register "speed_shift_enable" = "1"
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# Enable DPTF
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register "dptf_enable" = "1"
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# Disable DPTF
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register "dptf_enable" = "0"
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# FSP Configuration
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register "ProbelessTrace" = "0"
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@ -81,19 +81,21 @@ chip soc/intel/skylake
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register "pirqh_routing" = "PCH_IRQ11"
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# VR Settings Configuration for 4 Domains
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#+----------------+-------+-------+-------------+-------+
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#| Domain/Setting | SA | IA | GT Unsliced | GT |
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#+----------------+-------+-------+-------------+-------+
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#| Psi1Threshold | 20A | 20A | 20A | 20A |
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#| Psi2Threshold | 4A | 5A | 5A | 5A |
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#| Psi3Threshold | 1A | 1A | 1A | 1A |
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#| Psi3Enable | 1 | 1 | 1 | 1 |
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#| Psi4Enable | 1 | 1 | 1 | 1 |
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#| ImonSlope | 0 | 0 | 0 | 0 |
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#| ImonOffset | 0 | 0 | 0 | 0 |
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#| IccMax | 7A | 34A | 35A | 35A |
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#| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V |
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#+----------------+-------+-------+-------------+-------+
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#+----------------+-----------+-----------+-------------+----------+
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#| Domain/Setting | SA | IA | GT Unsliced | GT |
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#+----------------+-----------+-----------+-------------+----------+
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#| Psi1Threshold | 20A | 20A | 20A | 20A |
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#| Psi2Threshold | 4A | 5A | 5A | 5A |
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#| Psi3Threshold | 1A | 1A | 1A | 1A |
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#| Psi3Enable | 1 | 1 | 1 | 1 |
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#| Psi4Enable | 1 | 1 | 1 | 1 |
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#| ImonSlope | 0 | 0 | 0 | 0 |
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#| ImonOffset | 0 | 0 | 0 | 0 |
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#| IccMax | 7A | 34A | 35A | 35A |
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#| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V |
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#| AC LoadLine | 15 mOhm | 5.7 mOhm | 5.2 mOhm | 5.2 mOhm |
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#| DC LoadLine | 14.3 mOhm | 4.83 mOhm | 4.2 mOhm | 4.2 mOhm |
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#+----------------+-----------+-----------+-------------+----------+
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register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
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.vr_config_enable = 1,
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.psi1threshold = VR_CFG_AMP(20),
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@ -105,6 +107,8 @@ chip soc/intel/skylake
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.imon_offset = 0x0,
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.icc_max = VR_CFG_AMP(7),
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.voltage_limit = 1520,
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.ac_loadline = 1500,
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.dc_loadline = 1430,
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}"
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register "domain_vr_config[VR_IA_CORE]" = "{
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@ -118,6 +122,8 @@ chip soc/intel/skylake
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.imon_offset = 0x0,
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.icc_max = VR_CFG_AMP(34),
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.voltage_limit = 1520,
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.ac_loadline = 570,
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.dc_loadline = 483,
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}"
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register "domain_vr_config[VR_GT_UNSLICED]" = "{
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@ -131,6 +137,8 @@ chip soc/intel/skylake
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.imon_offset = 0x0,
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.icc_max = VR_CFG_AMP(35),
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.voltage_limit = 1520,
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.ac_loadline = 520,
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.dc_loadline = 420,
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}"
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register "domain_vr_config[VR_GT_SLICED]" = "{
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@ -144,6 +152,8 @@ chip soc/intel/skylake
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.imon_offset = 0x0,
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.icc_max = VR_CFG_AMP(35),
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.voltage_limit = 1520,
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.ac_loadline = 520,
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.dc_loadline = 420,
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}"
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# Enable Root Ports 5 and 9
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@ -31,8 +31,8 @@ chip soc/intel/skylake
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# Enable "Intel Speed Shift Technology"
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register "speed_shift_enable" = "1"
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# Enable DPTF
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register "dptf_enable" = "1"
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# Disable DPTF
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register "dptf_enable" = "0"
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# FSP Configuration
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register "ProbelessTrace" = "0"
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@ -81,19 +81,21 @@ chip soc/intel/skylake
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register "pirqh_routing" = "PCH_IRQ11"
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# VR Settings Configuration for 4 Domains
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#+----------------+-------+-------+-------------+-------+
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#| Domain/Setting | SA | IA | GT Unsliced | GT |
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#+----------------+-------+-------+-------------+-------+
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#| Psi1Threshold | 20A | 20A | 20A | 20A |
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#| Psi2Threshold | 4A | 5A | 5A | 5A |
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#| Psi3Threshold | 1A | 1A | 1A | 1A |
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#| Psi3Enable | 1 | 1 | 1 | 1 |
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#| Psi4Enable | 1 | 1 | 1 | 1 |
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#| ImonSlope | 0 | 0 | 0 | 0 |
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#| ImonOffset | 0 | 0 | 0 | 0 |
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#| IccMax | 7A | 34A | 35A | 35A |
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#| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V |
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#+----------------+-------+-------+-------------+-------+
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#+----------------+-----------+-----------+-------------+----------+
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#| Domain/Setting | SA | IA | GT Unsliced | GT |
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#+----------------+-----------+-----------+-------------+----------+
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#| Psi1Threshold | 20A | 20A | 20A | 20A |
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#| Psi2Threshold | 4A | 5A | 5A | 5A |
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#| Psi3Threshold | 1A | 1A | 1A | 1A |
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#| Psi3Enable | 1 | 1 | 1 | 1 |
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#| Psi4Enable | 1 | 1 | 1 | 1 |
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#| ImonSlope | 0 | 0 | 0 | 0 |
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#| ImonOffset | 0 | 0 | 0 | 0 |
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#| IccMax | 7A | 34A | 35A | 35A |
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#| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V |
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#| AC LoadLine | 15 mOhm | 5.7 mOhm | 5.2 mOhm | 5.2 mOhm |
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#| DC LoadLine | 14.3 mOhm | 4.83 mOhm | 4.2 mOhm | 4.2 mOhm |
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#+----------------+-----------+-----------+-------------+----------+
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register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
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.vr_config_enable = 1,
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.psi1threshold = VR_CFG_AMP(20),
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@ -105,6 +107,8 @@ chip soc/intel/skylake
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.imon_offset = 0x0,
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.icc_max = VR_CFG_AMP(7),
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.voltage_limit = 1520,
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.ac_loadline = 1500,
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.dc_loadline = 1430,
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}"
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register "domain_vr_config[VR_IA_CORE]" = "{
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@ -118,6 +122,8 @@ chip soc/intel/skylake
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.imon_offset = 0x0,
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.icc_max = VR_CFG_AMP(34),
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.voltage_limit = 1520,
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.ac_loadline = 570,
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.dc_loadline = 483,
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}"
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register "domain_vr_config[VR_GT_UNSLICED]" = "{
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@ -131,6 +137,8 @@ chip soc/intel/skylake
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.imon_offset = 0x0,
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.icc_max = VR_CFG_AMP(35),
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.voltage_limit = 1520,
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.ac_loadline = 520,
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.dc_loadline = 420,
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}"
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register "domain_vr_config[VR_GT_SLICED]" = "{
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@ -144,6 +152,8 @@ chip soc/intel/skylake
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.imon_offset = 0x0,
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.icc_max = VR_CFG_AMP(35),
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.voltage_limit = 1520,
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.ac_loadline = 520,
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.dc_loadline = 420,
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}"
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# Enable Root Ports 5 and 9
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