soc/cavium: Enable DRAM test
Enable fast or extended DRAM test based on devicetree setting. The fast DRAM test takes less than a second, while the extended runs about 1 minute. Tested on Cavium Soc. Change-Id: I6a375f3d4c5cea7c3c0cd4592287f3f85dc7d3cf Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/27103 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
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@ -20,6 +20,7 @@
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#include <bdk-devicetree.h>
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const struct bdk_devicetree_key_value devtree[] = {
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{"DDR-TEST-BOOT", "1"},
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{"DDR-CONFIG-DQX-CTL", "0x4"},
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{"DDR-CONFIG-WODT-MASK.RANKS2.DIMMS2", "0xc0c0303"},
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{"DDR-CONFIG-WODT-MASK.RANKS4.DIMMS1", "0x1030203"},
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@ -58,30 +58,38 @@ void sdram_init(void)
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/* See if we should test this node's DRAM during boot */
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int test_dram = bdk_config_get_int(BDK_CONFIG_DRAM_BOOT_TEST, 0);
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if (test_dram) {
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if (test_dram == 1) {
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static const u8 tests[] = {13, 0, 1};
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for (size_t i = 0; i < ARRAY_SIZE(tests); i++) {
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/* Run the address test to make sure DRAM works */
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if (bdk_dram_test(tests[i], 4 * MiB,
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sdram_size_mb() * MiB - 4 * MiB,
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BDK_DRAM_TEST_NO_STATS |
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BDK_DRAM_TEST_NODE0)) {
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printk(BIOS_CRIT, "%s: Failed DRAM test.\n",
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__func__);
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}
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bdk_watchdog_poke();
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}
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} else {
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/* Run the address test to make sure DRAM works */
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if (bdk_dram_test(13, 0, 0x10000000000ull, BDK_DRAM_TEST_NO_STATS | (1<<0))) {
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if (bdk_dram_test(13, 4 * MiB,
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sdram_size_mb() * MiB - 4 * MiB,
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BDK_DRAM_TEST_NO_STATS |
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BDK_DRAM_TEST_NODE0)) {
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/**
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* FIXME(dhendrix): This should be handled by mainboard code since we
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* don't necessarily have a BMC to report to. Also, we need to figure out
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* if we need to keep going as to avoid getting into a boot loop.
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* FIXME(dhendrix): This should be handled by mainboard
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* code since we don't necessarily have a BMC to report
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* to. Also, we need to figure out if we need to keep
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* going as to avoid getting into a boot loop.
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*/
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// bdk_boot_status(BDK_BOOT_STATUS_REQUEST_POWER_CYCLE);
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printk(BIOS_ERR, "%s: Failed DRAM test.\n", __func__);
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printk(BIOS_CRIT, "%s: Failed DRAM test.\n", __func__);
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}
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bdk_watchdog_poke();
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/* Put other node core back in reset */
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if (0 != bdk_numa_master())
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BDK_CSR_WRITE(0, BDK_RST_PP_RESET, -1);
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/* Clear DRAM */
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uint64_t skip = 0;
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if (0 == bdk_numa_master())
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skip = bdk_dram_get_top_of_bdk();
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void *base = bdk_phys_to_ptr(bdk_numa_get_address(0, skip));
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bdk_zero_memory(base, ((uint64_t)mbytes << 20) - skip);
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bdk_watchdog_poke();
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}
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bdk_watchdog_poke();
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/* Unlock L2 now that DRAM works */
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if (0 == bdk_numa_master()) {
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uint64_t l2_size = bdk_l2c_get_cache_size_bytes(0);
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