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mb/intel/adlrvp: Enable Hybrid storage mode 

TEST=Build and test booting ADL RVP form NVMe and Optane
localhost ~ # lspci -d :f1a6
Show all the NVMe devices and be really verbose
localhost ~ # lspci -vvvd :f1a6
Print PCIe lane capabilities and configurations for all the NVMe devices.

Change-Id: I0a04b23b17df574d4fa3bae233ca40cd3b104201
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46420
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Subrata Banik 2020-10-14 22:12:12 +05:30
parent 6147314344
commit 3f561a8e08
1 changed files with 2 additions and 0 deletions
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src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb
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@ -61,6 +61,8 @@ chip soc/intel/alderlake
# Enable PCH PCIE RP 11 for optane
register "PcieRpEnable[10]" = "1"
# Hybrid storage mode
register "HybridStorageMode" = "1"
# Enable CPU PCIE RP 1 using PEG CLK 0
register "PcieClkSrcUsage[0]" = "0x40"