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mb/system76/lemp9: move LPC options to the devicetree 

Change-Id: I7b7acdc51c848541fb39926bc8de1115c026dd05
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45496
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Michael Niewöhner 2020-09-18 00:46:51 +02:00
parent 80bd8e43b0
commit 3f5bfbd4d1
1 changed files with 9 additions and 11 deletions
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20
src/mainboard/system76/lemp9/devicetree.cb
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@ -50,17 +50,6 @@ chip soc/intel/cannonlake
# Thermal
register "tcc_offset" = "12"
# LPC (soc/intel/cannonlake/lpc.c)
# LPC configuration from lspci -s 1f.0 -xxx
# Address 0x84: Decode 0x80 - 0x8F (Port 80)
register "gen1_dec" = "0x000c0081"
# Address 0x88: Decode 0x68 - 0x6F (PMC)
register "gen2_dec" = "0x00040069"
# Address 0x8C: Decode 0xE00 - 0xEFF (AP/EC command)
register "gen3_dec" = "0x00fc0E01"
# Address 0x90: Decode 0xF00 - 0xFFF (AP/EC debug)
register "gen4_dec" = "0x00fc0F01"
# PM Util (soc/intel/cannonlake/pmutil.c)
# GPE configuration
# Note that GPE events called out in ASL code rely on this
@ -193,6 +182,15 @@ chip soc/intel/cannonlake
device pci 1e.2 off end # GSPI #0
device pci 1e.3 off end # GSPI #1
device pci 1f.0 on # LPC Interface
# LPC configuration from lspci -s 1f.0 -xxx
# Address 0x84: Decode 0x80 - 0x8F (Port 80)
register "gen1_dec" = "0x000c0081"
# Address 0x88: Decode 0x68 - 0x6F (PMC)
register "gen2_dec" = "0x00040069"
# Address 0x8C: Decode 0xE00 - 0xEFF (AP/EC command)
register "gen3_dec" = "0x00fc0E01"
# Address 0x90: Decode 0xF00 - 0xFFF (AP/EC debug)
register "gen4_dec" = "0x00fc0F01"
chip drivers/pc80/tpm # TPM
device pnp 0c31.0 on end
end