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mb/google/sarien: Replace B0D4 with TCPU 

Replace B0D4 with TCPU for DPTF thermal sensor. This helps to
maintain consistency between coreboot and UEFI BIOS.

Change-Id: I024068c19160e1c08badef3d304ada14455c045f
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/31028
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Sumeet Pawnikar 2019-01-21 15:23:55 +05:30 committed by Duncan Laurie
parent 8adbec26be
commit 3f689ca24a
2 changed files with 8 additions and 8 deletions
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8
src/mainboard/google/sarien/variants/arcada/include/variant/acpi/dptf.asl
View File

@ -39,16 +39,16 @@
Name (DTRT, Package () {
/* CPU Throttle Effect on CPU */
Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 10, 0, 0, 0, 0 },
Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 10, 0, 0, 0, 0 },
/* CPU Throttle Effect on Skin (TSR0) */
Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 },
Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 },
/* CPU Throttle Effect on DDR (TSR1) */
Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR1, 100, 90, 0, 0, 0, 0 },
Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 100, 90, 0, 0, 0, 0 },
/* CPU Throttle Effect on Ambient (TSR2) */
Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 },
Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 },
})
Name (MPPC, Package ()

8
src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl
View File

@ -39,16 +39,16 @@
Name (DTRT, Package () {
/* CPU Throttle Effect on CPU */
Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 10, 0, 0, 0, 0 },
Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 10, 0, 0, 0, 0 },
/* CPU Throttle Effect on Skin (TSR0) */
Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 },
Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 },
/* CPU Throttle Effect on DDR (TSR1) */
Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR1, 100, 90, 0, 0, 0, 0 },
Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 100, 90, 0, 0, 0, 0 },
/* CPU Throttle Effect on Ambient (TSR2) */
Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 },
Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 },
})
Name (MPPC, Package ()