diff --git a/src/mainboard/asus/p2b-ds/romstage.c b/src/mainboard/asus/p2b-ds/romstage.c
index 038e5edfaf..36f45a0d0a 100644
--- a/src/mainboard/asus/p2b-ds/romstage.c
+++ b/src/mainboard/asus/p2b-ds/romstage.c
@@ -24,11 +24,6 @@
 
 #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)
 
-int spd_read_byte(unsigned int device, unsigned int address)
-{
-	return smbus_read_byte(device, address);
-}
-
 void mainboard_romstage_entry(void)
 {
 	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
diff --git a/src/mainboard/asus/p2b-ls/romstage.c b/src/mainboard/asus/p2b-ls/romstage.c
index a4f1671806..87cb7531c7 100644
--- a/src/mainboard/asus/p2b-ls/romstage.c
+++ b/src/mainboard/asus/p2b-ls/romstage.c
@@ -25,11 +25,6 @@
 
 #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)
 
-int spd_read_byte(unsigned int device, unsigned int address)
-{
-	return smbus_read_byte(device, address);
-}
-
 void mainboard_romstage_entry(void)
 {
 	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
diff --git a/src/mainboard/asus/p2b/romstage.c b/src/mainboard/asus/p2b/romstage.c
index 805fc94152..8cbc59646d 100644
--- a/src/mainboard/asus/p2b/romstage.c
+++ b/src/mainboard/asus/p2b/romstage.c
@@ -24,11 +24,6 @@
 
 #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)
 
-int spd_read_byte(unsigned int device, unsigned int address)
-{
-	return smbus_read_byte(device, address);
-}
-
 void mainboard_romstage_entry(void)
 {
 	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
diff --git a/src/mainboard/asus/p3b-f/romstage.c b/src/mainboard/asus/p3b-f/romstage.c
index 8e254baa93..e9c41b1a95 100644
--- a/src/mainboard/asus/p3b-f/romstage.c
+++ b/src/mainboard/asus/p3b-f/romstage.c
@@ -27,11 +27,6 @@
 /* FIXME: The ASUS P3B-F has a Winbond W83977EF, actually. */
 #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)
 
-int spd_read_byte(unsigned int device, unsigned int address)
-{
-	return smbus_read_byte(device, address);
-}
-
 /*
  * ASUS P3B-F specific SPD enable magic.
  *
diff --git a/src/northbridge/intel/i440bx/raminit.c b/src/northbridge/intel/i440bx/raminit.c
index 28b22ec675..08019880b7 100644
--- a/src/northbridge/intel/i440bx/raminit.c
+++ b/src/northbridge/intel/i440bx/raminit.c
@@ -25,6 +25,8 @@
 #include "i440bx.h"
 #include "raminit.h"
 
+#include <southbridge/intel/i82371eb/i82371eb.h>
+
 /*
  * Macros and definitions
  */
@@ -650,7 +652,7 @@ static void spd_enable_refresh(void)
 	reg = pci_read_config8(NB, DRAMC);
 
 	for (i = 0; i < DIMM_SOCKETS; i++) {
-		value = spd_read_byte(DIMM0 + i, SPD_REFRESH);
+		value = smbus_read_byte(DIMM0 + i, SPD_REFRESH);
 		if (value < 0)
 			continue;
 		reg = (reg & 0xf8) | refresh_rate_map[(value & 0x7f)];
@@ -694,8 +696,8 @@ static struct dimm_size spd_get_dimm_size(unsigned int device)
 	struct dimm_size sz;
 	int i, module_density, dimm_banks;
 	sz.side1 = 0;
-	module_density = spd_read_byte(device, SPD_DENSITY_OF_EACH_ROW_ON_MODULE);
-	dimm_banks = spd_read_byte(device, SPD_NUM_DIMM_BANKS);
+	module_density = smbus_read_byte(device, SPD_DENSITY_OF_EACH_ROW_ON_MODULE);
+	dimm_banks = smbus_read_byte(device, SPD_NUM_DIMM_BANKS);
 
 	/* Find the size of side1. */
 	/* Find the larger value. The larger value is always side1. */
@@ -780,7 +782,7 @@ static void set_dram_row_attributes(void)
 		nbxecc >>= 2;
 
 		/* First check if a DIMM is actually present. */
-		value = spd_read_byte(device, SPD_MEMORY_TYPE);
+		value = smbus_read_byte(device, SPD_MEMORY_TYPE);
 		/* This is 440BX! We do EDO too! */
 		if (value == SPD_MEMORY_TYPE_EDO
 			|| value == SPD_MEMORY_TYPE_SDRAM) {
@@ -801,21 +803,21 @@ static void set_dram_row_attributes(void)
 			dra = 0;
 
 			/* Columns */
-			col = spd_read_byte(device, SPD_NUM_COLUMNS);
+			col = smbus_read_byte(device, SPD_NUM_COLUMNS);
 
 			/*
 			 * Is this an ECC DIMM? Actually will be a 2 if so.
 			 * TODO: Other register than NBXCFG also needs this
 			 * ECC information.
 			 */
-			value = spd_read_byte(device, SPD_DIMM_CONFIG_TYPE);
+			value = smbus_read_byte(device, SPD_DIMM_CONFIG_TYPE);
 
 			/* Data width */
-			width = spd_read_byte(device, SPD_MODULE_DATA_WIDTH_LSB);
+			width = smbus_read_byte(device, SPD_MODULE_DATA_WIDTH_LSB);
 
 			/* Exclude error checking data width from page size calculations */
 			if (value) {
-				value = spd_read_byte(device,
+				value = smbus_read_byte(device,
 					SPD_ERROR_CHECKING_SDRAM_WIDTH);
 				width -= value;
 				/* ### ECC */
@@ -831,7 +833,7 @@ static void set_dram_row_attributes(void)
 			 * By registered, only the address and control lines need to be, which
 			 * we can tell by reading SPD byte 21, bit 1.
 			 */
-			value = spd_read_byte(device, SPD_MODULE_ATTRIBUTES);
+			value = smbus_read_byte(device, SPD_MODULE_ATTRIBUTES);
 
 			PRINT_DEBUG("DIMM is ");
 			if ((value & MODULE_REGISTERED) == 0) {
@@ -847,12 +849,12 @@ static void set_dram_row_attributes(void)
 			dra = (value >> 13);
 
 			/* Number of banks of DIMM (single or double sided). */
-			value = spd_read_byte(device, SPD_NUM_DIMM_BANKS);
+			value = smbus_read_byte(device, SPD_NUM_DIMM_BANKS);
 
 			/* Once we have dra, col is done and can be reused.
 			 * So it's reused for number of banks.
 			 */
-			col = spd_read_byte(device, SPD_NUM_BANKS_PER_SDRAM);
+			col = smbus_read_byte(device, SPD_NUM_BANKS_PER_SDRAM);
 
 			if (value == 1) {
 				/*
diff --git a/src/northbridge/intel/i440bx/raminit.h b/src/northbridge/intel/i440bx/raminit.h
index 23299d1dd6..347c1fecd7 100644
--- a/src/northbridge/intel/i440bx/raminit.h
+++ b/src/northbridge/intel/i440bx/raminit.h
@@ -24,7 +24,6 @@ void enable_spd(void);
 void disable_spd(void);
 
 /* Function prototypes. */
-int spd_read_byte(unsigned int device, unsigned int address);
 void sdram_set_registers(void);
 void sdram_set_spd_registers(void);
 void sdram_enable(void);