soc/intel/alderlake: Add Alder Lake P IGD device IDs
This patch adds additional IGD device IDs as per document 638514. BUG=b:216420554 TEST=coreboot is able to probe the IGD device during PCI enumeration. Change-Id: I0cafe92581c454da5e4aeafd7ad52f0e65370b11 Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61441 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -3902,6 +3902,9 @@
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#define PCI_DEVICE_ID_INTEL_ADL_P_GT2_4 0x46a8
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#define PCI_DEVICE_ID_INTEL_ADL_P_GT2_5 0x46b3
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#define PCI_DEVICE_ID_INTEL_ADL_P_GT2_6 0x46a6
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#define PCI_DEVICE_ID_INTEL_ADL_P_GT2_7 0x4628
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#define PCI_DEVICE_ID_INTEL_ADL_P_GT2_8 0x46b1
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#define PCI_DEVICE_ID_INTEL_ADL_P_GT2_9 0x4626
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#define PCI_DEVICE_ID_INTEL_ADL_S_GT1 0x4680
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#define PCI_DEVICE_ID_INTEL_ADL_M_GT1 0x46c0
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#define PCI_DEVICE_ID_INTEL_ADL_M_GT2 0x46aa
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@ -115,6 +115,9 @@ static struct {
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{ PCI_DEVICE_ID_INTEL_ADL_P_GT2_4, "Alderlake P GT2" },
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{ PCI_DEVICE_ID_INTEL_ADL_P_GT2_5, "Alderlake P GT2" },
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{ PCI_DEVICE_ID_INTEL_ADL_P_GT2_6, "Alderlake P GT2" },
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{ PCI_DEVICE_ID_INTEL_ADL_P_GT2_7, "Alderlake P GT2" },
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{ PCI_DEVICE_ID_INTEL_ADL_P_GT2_8, "Alderlake P GT2" },
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{ PCI_DEVICE_ID_INTEL_ADL_P_GT2_9, "Alderlake P GT2" },
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{ PCI_DEVICE_ID_INTEL_ADL_M_GT1, "Alderlake M GT1" },
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{ PCI_DEVICE_ID_INTEL_ADL_M_GT2, "Alderlake M GT2" },
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{ PCI_DEVICE_ID_INTEL_ADL_M_GT3, "Alderlake M GT3" },
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@ -307,6 +307,9 @@ static const unsigned short pci_device_ids[] = {
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PCI_DEVICE_ID_INTEL_ADL_P_GT2_4,
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PCI_DEVICE_ID_INTEL_ADL_P_GT2_5,
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PCI_DEVICE_ID_INTEL_ADL_P_GT2_6,
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PCI_DEVICE_ID_INTEL_ADL_P_GT2_7,
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PCI_DEVICE_ID_INTEL_ADL_P_GT2_8,
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PCI_DEVICE_ID_INTEL_ADL_P_GT2_9,
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PCI_DEVICE_ID_INTEL_ADL_S_GT1,
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PCI_DEVICE_ID_INTEL_ADL_M_GT1,
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PCI_DEVICE_ID_INTEL_ADL_M_GT2,
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