nb/intel/x4x/raminit: Add DDR3 enhanced mode and power settings

Change-Id: I9d34154d3ac1dd1e5400d692d4dcce70d95662c8
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19917
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Arthur Heymans 2017-05-25 19:54:49 +02:00 committed by Martin Roth
parent b4a78045d5
commit 3fa103a602
3 changed files with 136 additions and 27 deletions

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@ -1800,7 +1800,10 @@ static void set_enhanced_mode(struct sysinfo *s)
MCHBAR32(0xfc4) = 0xfe22244;
MCHBAR8(0x12f) = 0x5c;
MCHBAR8(0xfb0) = (MCHBAR8(0xfb0) & ~1) | 1;
if (s->selected_timings.mem_clk <= MEM_CLOCK_800MHz)
MCHBAR8(0x12f) = MCHBAR8(0x12f) | 0x2;
else
MCHBAR8(0x12f) = MCHBAR8(0x12f) & 0x2;
MCHBAR8(0x6c0) = (MCHBAR8(0x6c0) & ~0xf0) | 0xa0;
MCHBAR32(0xfa8) = 0x30d400;
@ -1837,8 +1840,10 @@ static void power_settings(struct sysinfo *s)
u8 twl = 0;
u16 x264, x23c;
if (s->spd_type == DDR2) {
twl = s->selected_timings.CAS - 1;
x264 = 0x78;
switch (s->selected_timings.mem_clk) {
default:
case MEM_CLOCK_667MHz:
@ -1862,6 +1867,30 @@ static void power_settings(struct sysinfo *s)
}
reg3 = 0x232;
reg4 = 0x2864;
} else { /* DDR3 */
int ddr3_idx = s->selected_timings.mem_clk - MEM_CLOCK_800MHz;
int cas_idx = s->selected_timings.CAS - 5;
twl = s->selected_timings.mem_clk - MEM_CLOCK_800MHz + 5;
reg1 = ddr3_c2_tab[s->nmode - 1][ddr3_idx][cas_idx][0];
reg2 = ddr3_c2_tab[s->nmode - 1][ddr3_idx][cas_idx][1];
reg3 = 0x764;
reg4 = 0x78c8;
x264 = ddr3_c2_x264[ddr3_idx][cas_idx];
x23c = ddr3_c2_x23c[ddr3_idx][cas_idx];
switch (s->selected_timings.mem_clk) {
case MEM_CLOCK_800MHz:
default:
clkgate = 0x280000;
break;
case MEM_CLOCK_1066MHz:
clkgate = 0x350000;
break;
case MEM_CLOCK_1333MHz:
clkgate = 0xff0000;
break;
}
}
if (CHANNEL_IS_POPULATED(s->dimms, 0) && CHANNEL_IS_POPULATED(s->dimms, 1))
MCHBAR32(0x14) = 0x0010461f;
@ -1918,10 +1947,6 @@ static void power_settings(struct sysinfo *s)
MCHBAR32(0x110c) = 0x100;
MCHBAR32(0x1110) = 0x10810350 & ~0x78;
MCHBAR32(0x1114) = 0;
if (s->selected_timings.mem_clk == MEM_CLOCK_667MHz)
twl = 5;
else
twl = 6;
x592 = 0xff;
if (pci_read_config8(PCI_DEV(0, 0, 0), 0x8) < 3)
x592 = ~0x4;

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@ -288,3 +288,84 @@ const u8 ddr3_emrs1_rtt_nom_config[16][4] = { /* [Config][Rank] */
{0x81, 0x81, 0x81, 0x00}, /* 8D_16S */
{0x81, 0x00, 0x81, 0x00}, /* 16S_16S */
};
const u32 ddr3_c2_tab[2][3][6][2] = { /* [n-mode][ddr3 freq][CAS][reg] */
/* 115h[15:0] 117h[23:0] */
{ /* 1N mode */
{ /* DDR3 800MHz */
{0x0189, 0x000aaa}, /* CAS = 5 */
{0x0189, 0x101aaa}, /* CAS = 6 */
},
{ /* DDR3 1067MHz */
{0x0000, 0x000000}, /* CAS = 5 - Not supported */
{0x0089, 0x000bbb}, /* CAS = 6 */
{0x0099, 0x101bbb}, /* CAS = 7 */
{0x0099, 0x202bbb} /* CAS = 8 */
},{ /* DDR3 1333 */
{0x0000, 0x000000}, /* CAS = 5 - Not supported */
{0x0000, 0x000000}, /* CAS = 6 - Not supported */
{0x0000, 0x000000}, /* CAS = 7 - Not supported */
{0x129a, 0x0078dc}, /* CAS = 8 */
{0x028a, 0x0078dc}, /* CAS = 9 */
{0x028a, 0x1088dc}, /* CAS = 10 */
},
},
{ /* 2N mode */
{ /* DDR3 800MHz */
{0x0189, 0x000aaa}, /* CAS = 5 */
{0x0189, 0x101aaa}, /* CAS = 6 */
{0x0000, 0x000000}, /* CAS = 7 - Not supported */
{0x0000, 0x000000} /* CAS = 8 - Not suppported */
},
{ /* DDR3 1067 */
{0x0000, 0x000000}, /* CAS = 5 - Not supported */
{0x0089, 0x000bbb}, /* CAS = 6 */
{0x0099, 0x101bbb}, /* CAS = 7 */
{0x0099, 0x202bbb} /* CAS = 8 */
},{ /* DDR3 1333MHz */
{0x0000, 0x000000}, /* CAS = 5 - Not supported */
{0x0000, 0x000000}, /* CAS = 6 - Not supported */
{0x0000, 0x000000}, /* CAS = 7 - Not supported */
{0x019a, 0x0078dc}, /* CAS = 8 */
{0x019a, 0x1088dc}, /* CAS = 9 */
{0x019a, 0x2098dc}, /* CAS = 10 */
},
}
};
const u8 ddr3_c2_x264[3][6] = { /* [freq][cas] */
/* DDR3 800MHz */
{0x78, /* CAS = 5 */
0x89}, /* CAS = 6 */
/* DDR3 1066 */
{0x00, /* CAS = 5 - Not supported */
0xff, /* CAS = 6 */
0x8a, /* CAS = 7 */
0x9a}, /* CAS = 8 */
/* DDR3 1333 */
{0x00, /* CAS = 5 - Not supported */
0x00, /* CAS = 6 - Not supported */
0xff, /* CAS = 7 - Not supported */
0xff, /* CAS = 8 */
0xff, /* CAS = 9 */
0xff}, /* CAS = 10 */
};
const u16 ddr3_c2_x23c[3][6]={ /* [freq][cas] */
/* DDR3 800MHz */
{0x9bbb, /* CAS = 5 */
0x8bbb}, /* CAS = 6 */
/* DDR3 1066MHz */
{0x0000, /* CAS = 5 - Not supported */
0x9baa, /* CAS = 6 */
0x8caa, /* CAS = 7 */
0x7daa}, /* CAS = 8 */
/* DDR3 1333MHz */
{0x0000, /* CAS = 5 - Not supported */
0x0000, /* CAS = 6 - Not supported */
0x0000, /* CAS = 7 - Not supported */
0xaecb, /* CAS = 8 */
0x9fcb, /* CAS = 9 */
0x8fcb}, /* CAS = 10 */
};

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@ -392,6 +392,9 @@ extern const struct dll_setting default_ddr3_800_dq[2][TOTAL_BYTELANES];
extern const struct dll_setting default_ddr3_1067_dq[2][TOTAL_BYTELANES];
extern const struct dll_setting default_ddr3_1333_dq[2][TOTAL_BYTELANES];
extern const u8 ddr3_emrs1_rtt_nom_config[16][4];
extern const u32 ddr3_c2_tab[2][3][6][2];
extern const u8 ddr3_c2_x264[3][6];
extern const u16 ddr3_c2_x23c[3][6];
struct acpi_rsdp;
#ifndef __SIMPLE_DEVICE__