nb/intel/x4x/raminit: Add DDR3 enhanced mode and power settings
Change-Id: I9d34154d3ac1dd1e5400d692d4dcce70d95662c8 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19917 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Arthur Heymans
Martin Roth
parent
b4a78045d5
commit
3fa103a602
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@ -1800,7 +1800,10 @@ static void set_enhanced_mode(struct sysinfo *s)
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MCHBAR32(0xfc4) = 0xfe22244;
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MCHBAR8(0x12f) = 0x5c;
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MCHBAR8(0xfb0) = (MCHBAR8(0xfb0) & ~1) | 1;
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MCHBAR8(0x12f) = MCHBAR8(0x12f) | 0x2;
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if (s->selected_timings.mem_clk <= MEM_CLOCK_800MHz)
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MCHBAR8(0x12f) = MCHBAR8(0x12f) | 0x2;
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else
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MCHBAR8(0x12f) = MCHBAR8(0x12f) & 0x2;
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MCHBAR8(0x6c0) = (MCHBAR8(0x6c0) & ~0xf0) | 0xa0;
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MCHBAR32(0xfa8) = 0x30d400;
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@ -1837,31 +1840,57 @@ static void power_settings(struct sysinfo *s)
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u8 twl = 0;
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u16 x264, x23c;
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twl = s->selected_timings.CAS - 1;
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x264 = 0x78;
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switch (s->selected_timings.mem_clk) {
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default:
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case MEM_CLOCK_667MHz:
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reg1 = 0x99;
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reg2 = 0x1048a9;
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clkgate = 0x230000;
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x23c = 0x7a89;
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break;
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case MEM_CLOCK_800MHz:
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if (s->selected_timings.CAS == 5) {
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reg1 = 0x19a;
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reg2 = 0x1048aa;
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} else {
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reg1 = 0x9a;
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reg2 = 0x2158aa;
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if (s->spd_type == DDR2) {
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twl = s->selected_timings.CAS - 1;
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x264 = 0x78;
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switch (s->selected_timings.mem_clk) {
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default:
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case MEM_CLOCK_667MHz:
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reg1 = 0x99;
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reg2 = 0x1048a9;
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clkgate = 0x230000;
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x23c = 0x7a89;
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break;
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case MEM_CLOCK_800MHz:
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if (s->selected_timings.CAS == 5) {
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reg1 = 0x19a;
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reg2 = 0x1048aa;
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} else {
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reg1 = 0x9a;
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reg2 = 0x2158aa;
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x264 = 0x89;
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}
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clkgate = 0x280000;
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x23c = 0x7b89;
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break;
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}
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reg3 = 0x232;
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reg4 = 0x2864;
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} else { /* DDR3 */
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int ddr3_idx = s->selected_timings.mem_clk - MEM_CLOCK_800MHz;
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int cas_idx = s->selected_timings.CAS - 5;
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twl = s->selected_timings.mem_clk - MEM_CLOCK_800MHz + 5;
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reg1 = ddr3_c2_tab[s->nmode - 1][ddr3_idx][cas_idx][0];
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reg2 = ddr3_c2_tab[s->nmode - 1][ddr3_idx][cas_idx][1];
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reg3 = 0x764;
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reg4 = 0x78c8;
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x264 = ddr3_c2_x264[ddr3_idx][cas_idx];
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x23c = ddr3_c2_x23c[ddr3_idx][cas_idx];
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switch (s->selected_timings.mem_clk) {
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case MEM_CLOCK_800MHz:
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default:
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clkgate = 0x280000;
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break;
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case MEM_CLOCK_1066MHz:
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clkgate = 0x350000;
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break;
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case MEM_CLOCK_1333MHz:
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clkgate = 0xff0000;
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break;
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}
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clkgate = 0x280000;
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x23c = 0x7b89;
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break;
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}
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reg3 = 0x232;
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reg4 = 0x2864;
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if (CHANNEL_IS_POPULATED(s->dimms, 0) && CHANNEL_IS_POPULATED(s->dimms, 1))
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MCHBAR32(0x14) = 0x0010461f;
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@ -1918,10 +1947,6 @@ static void power_settings(struct sysinfo *s)
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MCHBAR32(0x110c) = 0x100;
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MCHBAR32(0x1110) = 0x10810350 & ~0x78;
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MCHBAR32(0x1114) = 0;
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if (s->selected_timings.mem_clk == MEM_CLOCK_667MHz)
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twl = 5;
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else
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twl = 6;
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x592 = 0xff;
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if (pci_read_config8(PCI_DEV(0, 0, 0), 0x8) < 3)
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x592 = ~0x4;
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@ -288,3 +288,84 @@ const u8 ddr3_emrs1_rtt_nom_config[16][4] = { /* [Config][Rank] */
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{0x81, 0x81, 0x81, 0x00}, /* 8D_16S */
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{0x81, 0x00, 0x81, 0x00}, /* 16S_16S */
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};
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const u32 ddr3_c2_tab[2][3][6][2] = { /* [n-mode][ddr3 freq][CAS][reg] */
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/* 115h[15:0] 117h[23:0] */
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{ /* 1N mode */
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{ /* DDR3 800MHz */
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{0x0189, 0x000aaa}, /* CAS = 5 */
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{0x0189, 0x101aaa}, /* CAS = 6 */
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},
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{ /* DDR3 1067MHz */
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{0x0000, 0x000000}, /* CAS = 5 - Not supported */
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{0x0089, 0x000bbb}, /* CAS = 6 */
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{0x0099, 0x101bbb}, /* CAS = 7 */
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{0x0099, 0x202bbb} /* CAS = 8 */
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},{ /* DDR3 1333 */
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{0x0000, 0x000000}, /* CAS = 5 - Not supported */
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{0x0000, 0x000000}, /* CAS = 6 - Not supported */
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{0x0000, 0x000000}, /* CAS = 7 - Not supported */
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{0x129a, 0x0078dc}, /* CAS = 8 */
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{0x028a, 0x0078dc}, /* CAS = 9 */
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{0x028a, 0x1088dc}, /* CAS = 10 */
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},
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},
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{ /* 2N mode */
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{ /* DDR3 800MHz */
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{0x0189, 0x000aaa}, /* CAS = 5 */
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{0x0189, 0x101aaa}, /* CAS = 6 */
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{0x0000, 0x000000}, /* CAS = 7 - Not supported */
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{0x0000, 0x000000} /* CAS = 8 - Not suppported */
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},
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{ /* DDR3 1067 */
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{0x0000, 0x000000}, /* CAS = 5 - Not supported */
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{0x0089, 0x000bbb}, /* CAS = 6 */
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{0x0099, 0x101bbb}, /* CAS = 7 */
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{0x0099, 0x202bbb} /* CAS = 8 */
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},{ /* DDR3 1333MHz */
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{0x0000, 0x000000}, /* CAS = 5 - Not supported */
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{0x0000, 0x000000}, /* CAS = 6 - Not supported */
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{0x0000, 0x000000}, /* CAS = 7 - Not supported */
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{0x019a, 0x0078dc}, /* CAS = 8 */
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{0x019a, 0x1088dc}, /* CAS = 9 */
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{0x019a, 0x2098dc}, /* CAS = 10 */
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},
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}
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};
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const u8 ddr3_c2_x264[3][6] = { /* [freq][cas] */
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/* DDR3 800MHz */
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{0x78, /* CAS = 5 */
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0x89}, /* CAS = 6 */
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/* DDR3 1066 */
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{0x00, /* CAS = 5 - Not supported */
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0xff, /* CAS = 6 */
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0x8a, /* CAS = 7 */
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0x9a}, /* CAS = 8 */
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/* DDR3 1333 */
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{0x00, /* CAS = 5 - Not supported */
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0x00, /* CAS = 6 - Not supported */
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0xff, /* CAS = 7 - Not supported */
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0xff, /* CAS = 8 */
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0xff, /* CAS = 9 */
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0xff}, /* CAS = 10 */
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};
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const u16 ddr3_c2_x23c[3][6]={ /* [freq][cas] */
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/* DDR3 800MHz */
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{0x9bbb, /* CAS = 5 */
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0x8bbb}, /* CAS = 6 */
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/* DDR3 1066MHz */
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{0x0000, /* CAS = 5 - Not supported */
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0x9baa, /* CAS = 6 */
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0x8caa, /* CAS = 7 */
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0x7daa}, /* CAS = 8 */
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/* DDR3 1333MHz */
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{0x0000, /* CAS = 5 - Not supported */
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0x0000, /* CAS = 6 - Not supported */
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0x0000, /* CAS = 7 - Not supported */
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0xaecb, /* CAS = 8 */
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0x9fcb, /* CAS = 9 */
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0x8fcb}, /* CAS = 10 */
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};
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@ -392,6 +392,9 @@ extern const struct dll_setting default_ddr3_800_dq[2][TOTAL_BYTELANES];
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extern const struct dll_setting default_ddr3_1067_dq[2][TOTAL_BYTELANES];
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extern const struct dll_setting default_ddr3_1333_dq[2][TOTAL_BYTELANES];
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extern const u8 ddr3_emrs1_rtt_nom_config[16][4];
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extern const u32 ddr3_c2_tab[2][3][6][2];
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extern const u8 ddr3_c2_x264[3][6];
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extern const u16 ddr3_c2_x23c[3][6];
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struct acpi_rsdp;
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#ifndef __SIMPLE_DEVICE__
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