cpu/intel/slot_1: Cache romstage XIP execution
Change-Id: I19fc31a0fe71c5d0c6845a8680e267a0bf5f1a8f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37164 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Keith Hui <buurin@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -27,6 +27,7 @@ config SLOT_SPECIFIC_OPTIONS # dummy
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select UDELAY_TSC
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select TSC_MONOTONIC_TIMER
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select UNKNOWN_TSC_RATE
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select SETUP_XIP_CACHE
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config DCACHE_RAM_BASE
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hex
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