cpu/intel/slot_1: Cache romstage XIP execution

Change-Id: I19fc31a0fe71c5d0c6845a8680e267a0bf5f1a8f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37164
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Keith Hui <buurin@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/cpu/intel/slot_1/Kconfig

@@ -27,6 +27,7 @@ config SLOT_SPECIFIC_OPTIONS # dummy
 	select UDELAY_TSC
 	select TSC_MONOTONIC_TIMER
 	select UNKNOWN_TSC_RATE
+	select SETUP_XIP_CACHE
 
 config DCACHE_RAM_BASE
 	hex