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soc/intel/braswell: Put SERIRQ in quiet mode 

Cherry-pick from Chromium commit 1568761.

Original-Change-Id: If459c3cab8fb7ca13d8bff3173a94855ec2e2810
Original-Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Kevin K Wong <kevin.k.wong@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@google.com>
Original-Tested-by: Aseda Aboagye <aaboagye@chromium.org>

Change-Id: Ibb2e6d316adcfcc0d56d242501aac9c4c0bbdf62
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21173
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Hannah Williams 2017-03-22 16:33:36 -07:00 committed by Martin Roth
parent ad8669ef30
commit 3fa80a9c6f
2 changed files with 16 additions and 0 deletions
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3
src/soc/intel/braswell/include/soc/lpc.h
View File

@ -30,6 +30,9 @@
#define UART_CONT 0x80
#define RCBA 0xf0
/* Memory Mapped IO in LPC bridge */
#define SCNT 0x10
#define SCNT_MODE (1 << 7) /* When cleared, SERIRQ is in quiet mode */
#define RID_A_STEPPING_START 1
#define RID_B_STEPPING_START 5

13
src/soc/intel/braswell/southcluster.c
View File

@ -38,6 +38,18 @@
#include <soc/spi.h>
#include <spi-generic.h>
#include <stdint.h>
#include <reg_script.h>
static const struct reg_script ops[] = {
REG_MMIO_RMW32(ILB_BASE_ADDRESS + SCNT,
~SCNT_MODE, 0), /* put LPC SERIRQ in Quiet Mode */
REG_SCRIPT_END
};
static void enable_serirq_quiet_mode(void)
{
reg_script_run(ops);
}
static inline void
add_mmio_resource(device_t dev, int i, unsigned long addr, unsigned long size)
@ -503,6 +515,7 @@ static void finalize_chipset(void *unused)
write32(spi + LVSCC, cfg.lvscc | VCL);
}
spi_init();
enable_serirq_quiet_mode();
printk(BIOS_DEBUG, "Finalizing SMM.\n");
outb(APM_CNT_FINALIZE, APM_CNT);