soc/intel/braswell: Put SERIRQ in quiet mode
Cherry-pick from Chromium commit 1568761. Original-Change-Id: If459c3cab8fb7ca13d8bff3173a94855ec2e2810 Original-Signed-off-by: Hannah Williams <hannah.williams@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Kevin K Wong <kevin.k.wong@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@google.com> Original-Tested-by: Aseda Aboagye <aaboagye@chromium.org> Change-Id: Ibb2e6d316adcfcc0d56d242501aac9c4c0bbdf62 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21173 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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@ -30,6 +30,9 @@
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#define UART_CONT 0x80
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#define RCBA 0xf0
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/* Memory Mapped IO in LPC bridge */
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#define SCNT 0x10
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#define SCNT_MODE (1 << 7) /* When cleared, SERIRQ is in quiet mode */
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#define RID_A_STEPPING_START 1
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#define RID_B_STEPPING_START 5
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@ -38,6 +38,18 @@
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#include <soc/spi.h>
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#include <spi-generic.h>
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#include <stdint.h>
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#include <reg_script.h>
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static const struct reg_script ops[] = {
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REG_MMIO_RMW32(ILB_BASE_ADDRESS + SCNT,
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~SCNT_MODE, 0), /* put LPC SERIRQ in Quiet Mode */
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REG_SCRIPT_END
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};
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static void enable_serirq_quiet_mode(void)
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{
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reg_script_run(ops);
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}
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static inline void
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add_mmio_resource(device_t dev, int i, unsigned long addr, unsigned long size)
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@ -503,6 +515,7 @@ static void finalize_chipset(void *unused)
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write32(spi + LVSCC, cfg.lvscc | VCL);
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}
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spi_init();
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enable_serirq_quiet_mode();
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printk(BIOS_DEBUG, "Finalizing SMM.\n");
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outb(APM_CNT_FINALIZE, APM_CNT);
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