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rambi: mainboard EC - SCI and SMI fixes 

As rambi is a baytrail board it doesn't have a dedicated wake pin.
Therefore, one needs to enable the proper GPIO to wake up the sytem
before going into S3.

BUG=chrome-os-partner:23505
BRANCH=None
TEST=Put system into S3. Keyboard press created wake event. Also, typed
     'lidclose' on EC console while at recovery screen. Machine properly
     shutdown.

Change-Id: Ic67b6bce93d57c620f498505d83197e4ae34a07d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176392
Reviewed-on: http://review.coreboot.org/4959
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Aaron Durbin 2013-11-11 14:55:47 -06:00 committed by Aaron Durbin
parent 9f83e873f4
commit 3fbf671194
2 changed files with 11 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
src/mainboard/google/rambi/ec.c
View File

@ -42,6 +42,7 @@ void mainboard_ec_init(void)
} else { } else {
google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS | google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS |
MAINBOARD_EC_S5_WAKE_EVENTS); MAINBOARD_EC_S5_WAKE_EVENTS);
google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS);
} }
/* Clear wake events, these are enabled on entry to sleep */ /* Clear wake events, these are enabled on entry to sleep */

13
src/mainboard/google/rambi/mainboard_smi.c
View File

@ -28,6 +28,9 @@
#include <baytrail/nvs.h> #include <baytrail/nvs.h>
#include <baytrail/pmc.h> #include <baytrail/pmc.h>
/* The wake gpio is SUS_GPIO[0]. */
#define WAKE_GPIO_EN SUS_GPIO_EN0
int mainboard_io_trap_handler(int smif) int mainboard_io_trap_handler(int smif)
{ {
switch (smif) { switch (smif) {
@ -67,7 +70,7 @@ static uint8_t mainboard_smi_ec(void)
/* Go to S5 */ /* Go to S5 */
pm1_cnt = inl(pmbase + PM1_CNT); pm1_cnt = inl(pmbase + PM1_CNT);
pm1_cnt |= SLP_TYP | (SLP_TYP_S5 << SLP_TYP_SHIFT); pm1_cnt |= SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT);
outl(pm1_cnt, pmbase + PM1_CNT); outl(pm1_cnt, pmbase + PM1_CNT);
break; break;
} }
@ -75,9 +78,11 @@ static uint8_t mainboard_smi_ec(void)
return cmd; return cmd;
} }
void mainboard_smi_gpi(uint32_t gpi_sts) /* The entire 32-bit ALT_GPIO_SMI register is passed as a parameter. Note, that
* this includes the enable bits in the lower 16 bits. */
void mainboard_smi_gpi(uint32_t alt_gpio_smi)
{ {
if (gpi_sts & (1 << EC_SMI_GPI)) { if (alt_gpio_smi & (1 << EC_SMI_GPI)) {
/* Process all pending events */ /* Process all pending events */
while (mainboard_smi_ec() != 0); while (mainboard_smi_ec() != 0);
} }
@ -97,6 +102,8 @@ void mainboard_smi_sleep(uint8_t slp_typ)
/* Enable wake events */ /* Enable wake events */
google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS); google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS);
/* Enable wake pin in GPE block. */
enable_gpe(WAKE_GPIO_EN);
break; break;
case 5: case 5:
if (smm_get_gnvs()->s5u0 == 0) if (smm_get_gnvs()->s5u0 == 0)