From 3fca2c79224f402f11f0b5fac0c5b267c342f6de Mon Sep 17 00:00:00 2001
From: Tim Wawrzynczak <twawrzynczak@chromium.org>
Date: Tue, 10 Nov 2020 10:09:32 -0700
Subject: [PATCH] soc/intel/alderlake: Add PCIe root port wake sources to elog

Log PCIe root port wake events in the elog.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I2867b1fa12f639cd6c49a58f698b51b089e2b483
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47398
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
---
 src/soc/intel/alderlake/elog.c | 44 ++++++++++++++++++++++++++++++----
 1 file changed, 40 insertions(+), 4 deletions(-)

diff --git a/src/soc/intel/alderlake/elog.c b/src/soc/intel/alderlake/elog.c
index 8ec1107554..88bf34437b 100644
--- a/src/soc/intel/alderlake/elog.c
+++ b/src/soc/intel/alderlake/elog.c
@@ -2,11 +2,18 @@
 
 #include <bootstate.h>
 #include <console/console.h>
-#include <stdint.h>
+#include <device/pci_ops.h>
 #include <elog.h>
 #include <intelblocks/pmclib.h>
 #include <soc/pci_devs.h>
 #include <soc/pm.h>
+#include <stdint.h>
+#include <types.h>
+
+struct pme_map {
+	pci_devfn_t devfn;
+	unsigned int wake_source;
+};
 
 static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start)
 {
@@ -20,7 +27,36 @@ static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start)
 	}
 }
 
-static void pch_log_wake_source(const struct chipset_power_state *ps)
+static void pch_log_rp_wake_source(void)
+{
+	size_t i;
+
+	const struct pme_map pme_map[] = {
+		{ PCH_DEVFN_PCIE1,	ELOG_WAKE_SOURCE_PME_PCIE1 },
+		{ PCH_DEVFN_PCIE2,	ELOG_WAKE_SOURCE_PME_PCIE2 },
+		{ PCH_DEVFN_PCIE3,	ELOG_WAKE_SOURCE_PME_PCIE3 },
+		{ PCH_DEVFN_PCIE4,	ELOG_WAKE_SOURCE_PME_PCIE4 },
+		{ PCH_DEVFN_PCIE5,	ELOG_WAKE_SOURCE_PME_PCIE5 },
+		{ PCH_DEVFN_PCIE6,	ELOG_WAKE_SOURCE_PME_PCIE6 },
+		{ PCH_DEVFN_PCIE7,	ELOG_WAKE_SOURCE_PME_PCIE7 },
+		{ PCH_DEVFN_PCIE8,	ELOG_WAKE_SOURCE_PME_PCIE8 },
+		{ PCH_DEVFN_PCIE9,	ELOG_WAKE_SOURCE_PME_PCIE9 },
+		{ PCH_DEVFN_PCIE10,	ELOG_WAKE_SOURCE_PME_PCIE10 },
+		{ PCH_DEVFN_PCIE11,	ELOG_WAKE_SOURCE_PME_PCIE11 },
+		{ PCH_DEVFN_PCIE12,	ELOG_WAKE_SOURCE_PME_PCIE12 },
+	};
+
+	for (i = 0; i < MIN(CONFIG_MAX_ROOT_PORTS, ARRAY_SIZE(pme_map)); ++i) {
+		const struct device *dev = pcidev_path_on_root(pme_map[i].devfn);
+		if (!dev)
+			continue;
+
+		if (pci_dev_is_wake_source(dev))
+			elog_add_event_wake(pme_map[i].wake_source, 0);
+	}
+}
+
+static void pch_log_wake_source(struct chipset_power_state *ps)
 {
 	/* Power Button */
 	if (ps->pm1_sts & PWRBTN_STS)
@@ -30,9 +66,9 @@ static void pch_log_wake_source(const struct chipset_power_state *ps)
 	if (ps->pm1_sts & RTC_STS)
 		elog_add_event_wake(ELOG_WAKE_SOURCE_RTC, 0);
 
-	/* PCI Express (TODO: determine wake device) */
+	/* PCI Express */
 	if (ps->pm1_sts & PCIEXPWAK_STS)
-		elog_add_event_wake(ELOG_WAKE_SOURCE_PCIE, 0);
+		pch_log_rp_wake_source();
 
 	/* PME (TODO: determine wake device) */
 	if (ps->gpe0_sts[GPE_STD] & PME_STS)