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lynxpoint: expose pch_disable_devfn() 

The function to disable devices was formerly named
pch_hide_devfn(). This routine was doing more than hiding
devices. It was disabling them, i.e. turning them off.
Therefore, rename it to pch_disable_devfn(). Also, allow
external callers to this function.

Change-Id: Id5bb319d4e67892c02a39dff49e45b2811a2f016
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/59276
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4250
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
This commit is contained in:
Aaron Durbin 2013-06-19 13:20:37 -05:00 committed by Alexandru Gagniuc
parent c17aac32f2
commit 3fcd356464
2 changed files with 6 additions and 5 deletions
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10
src/southbridge/intel/lynxpoint/pch.c
View File

@ -92,7 +92,7 @@ static void pch_enable_d3hot(device_t dev)
} }
/* Set bit in Function Disble register to hide this device */ /* Set bit in Function Disble register to hide this device */
static void pch_hide_devfn(device_t dev) void pch_disable_devfn(device_t dev)
{ {
switch (dev->path.pci.devfn) { switch (dev->path.pci.devfn) {
case PCI_DEVFN(19, 0): /* Audio DSP */ case PCI_DEVFN(19, 0): /* Audio DSP */
@ -432,8 +432,8 @@ static void pch_pcie_enable(device_t dev)
/* Do not claim downstream transactions for PCIe ports */ /* Do not claim downstream transactions for PCIe ports */
new_rpfn |= RPFN_HIDE(PCI_FUNC(dev->path.pci.devfn)); new_rpfn |= RPFN_HIDE(PCI_FUNC(dev->path.pci.devfn));
/* Hide this device if possible */ /* Disable this device if possible */
pch_hide_devfn(dev); pch_disable_devfn(dev);
} else { } else {
int fn; int fn;
@ -491,8 +491,8 @@ void pch_enable(device_t dev)
PCI_COMMAND_MEMORY | PCI_COMMAND_IO); PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
pci_write_config32(dev, PCI_COMMAND, reg32); pci_write_config32(dev, PCI_COMMAND, reg32);
/* Hide this device if possible */ /* Disable this device if possible */
pch_hide_devfn(dev); pch_disable_devfn(dev);
} else { } else {
/* Enable SERR */ /* Enable SERR */
reg32 = pci_read_config32(dev, PCI_COMMAND); reg32 = pci_read_config32(dev, PCI_COMMAND);

1
src/southbridge/intel/lynxpoint/pch.h
View File

@ -162,6 +162,7 @@ void disable_gpe(u32 mask);
#include <arch/acpi.h> #include <arch/acpi.h>
#include "chip.h" #include "chip.h"
void pch_enable(device_t dev); void pch_enable(device_t dev);
void pch_disable_devfn(device_t dev);
u32 pch_iobp_read(u32 address); u32 pch_iobp_read(u32 address);
void pch_iobp_write(u32 address, u32 data); void pch_iobp_write(u32 address, u32 data);
void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue);