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mb/intel/adlrvp: Fix S0ix regression 

The following changes are needed to fix S0ix regression on RVP
1) Disable Clk src 3
2) Disable Ext FIVR settings

TEST=Boot adlrvp to OS, confirm S0ix is working.

Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: I0b8b76b5527d8b80776cb7588ce6b12281af7882
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58178
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
This commit is contained in:
Meera Ravindranath 2021-10-07 20:59:43 +05:30 committed by Felix Held
parent df99e57289
commit 3fd39467b5
1 changed files with 0 additions and 21 deletions
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21
src/mainboard/intel/adlrvp/devicetree.cb
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@ -83,12 +83,6 @@ chip soc/intel/alderlake
.clk_src = 0,
}"
# Enable CPU PCIE RP 2 using CLK 3
register "cpu_pcie_rp[CPU_RP(2)]" = "{
.clk_req = 3,
.clk_src = 3,
}"
# Enable CPU PCIE RP 3 using CLK 4
register "cpu_pcie_rp[CPU_RP(3)]" = "{
.clk_req = 4,
@ -187,21 +181,6 @@ chip soc/intel/alderlake
},
}"
# FIVR configurations
register "ext_fivr_settings" = "{
.configure_ext_fivr = 1,
.v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX,
.vnn_enable_bitmap = FIVR_ENABLE_ALL_SX,
.vnn_sx_enable_bitmap = FIVR_ENABLE_ALL_SX,
.v1p05_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL,
.vnn_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL,
.v1p05_voltage_mv = 1050,
.vnn_voltage_mv = 1050,
.vnn_sx_voltage_mv = 1050,
.v1p05_icc_max_ma = 500,
.vnn_icc_max_ma = 500,
}"
device domain 0 on
device ref pcie5 on end
device ref igpu on end