mb/google/brya/var/omnigul: Add memory config

Configure the rcomp, dqs and dq tables based on the schematic.

BUG=b:264340545
BRANCH=firmware-brya-14505.B
TEST=FW_NAME=omnigul emerge-brya coreboot

Change-Id: I82ca8aa9c3535983d5c506c15dbc69e7be926fa0
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71930
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Marx Wang <marx.wang@intel.com>

src/mainboard/google/brya/variants/omnigul/Makefile.inc

@@ -4,3 +4,5 @@ bootblock-y += gpio.c
 ramstage-y += gpio.c
 
 romstage-y += gpio.c
+
+romstage-y += memory.c

src/mainboard/google/brya/variants/omnigul/memory.c

@@ -0,0 +1,115 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <gpio.h>
+#include <soc/romstage.h>
+
+static const struct mb_cfg baseboard_memcfg = {
+	.type = MEM_TYPE_LP5X,
+
+	.rcomp = {
+		/* Baseboard uses only 100ohm Rcomp resistors */
+		.resistor = 100,
+	},
+
+	/* DQ byte map */
+	.lpx_dq_map = {
+		.ddr0 = {
+			.dq0 = {  0,  3,  2,  1,  6,  4,  5,  7 },
+			.dq1 = { 14, 12, 13, 15, 11,  8, 10,  9 },
+		},
+		.ddr1 = {
+			.dq0 = {  1,  0,  2,  3,  6,  4,  7,  5 },
+			.dq1 = { 15, 13, 12, 14,  8, 11, 10,  9 },
+		},
+		.ddr2 = {
+			.dq0 = {  2,  1,  3,  0,  7,  6,  4,  5 },
+			.dq1 = { 14, 12, 13, 15,  8,  9, 10, 11 },
+		},
+		.ddr3 = {
+			.dq0 = {  1,  2,  3,  0,  6,  4,  7,  5 },
+			.dq1 = { 13, 15, 12, 14,  8,  11, 10, 9 },
+		},
+		.ddr4 = {
+			.dq0 = {  2,  3,  0,  1,  6,  5,  7,  4 },
+			.dq1 = { 14, 12, 13, 15,  8, 10,  9, 11 },
+		},
+		.ddr5 = {
+			.dq0 = {  1,  2,  3,  0,  6,  4,  7,  5 },
+			.dq1 = { 15, 13, 12, 14, 11,  9, 10,  8 },
+		},
+		.ddr6 = {
+			.dq0 = {  3,  1,  2,  0,  5,  7,  6,  4 },
+			.dq1 = { 15, 13, 14, 12, 10,  9, 11,  8 },
+		},
+		.ddr7 = {
+			.dq0 = {  2,  3,  1,  0,  5,  4,  7,  6 },
+			.dq1 = { 14, 15, 10, 11,  13, 8,  9, 12 },
+		},
+	},
+
+	/* DQS CPU<>DRAM map */
+	.lpx_dqs_map = {
+		.ddr0 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr1 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr2 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr3 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr4 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr5 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr6 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr7 = { .dqs0 = 0, .dqs1 = 1 },
+	},
+
+	.lp5x_config = {
+		.ccc_config = 0xff,
+	},
+
+	.ect = 1, /* Early Command Training */
+
+	.UserBd = BOARD_TYPE_ULT_ULX,
+};
+
+const struct mb_cfg *variant_memory_params(void)
+{
+	return &baseboard_memcfg;
+}
+
+int variant_memory_sku(void)
+{
+	/*
+	 * Memory configuration board straps
+	 * GPIO_MEM_CONFIG_0	GPP_E11
+	 * GPIO_MEM_CONFIG_1	GPP_E2
+	 * GPIO_MEM_CONFIG_2	GPP_E1
+	 * GPIO_MEM_CONFIG_3    GPP_E12
+	 */
+	gpio_t spd_gpios[] = {
+		GPP_E11,
+		GPP_E2,
+		GPP_E1,
+		GPP_E12,
+	};
+
+	return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));
+}
+
+bool variant_is_half_populated(void)
+{
+	/*
+	 * Ideally half_populated is used in platforms with multiple channels to
+	 * enable only one half of the channel. Alder Lake N has single channel,
+	 * and it would require for new structures to be defined in meminit block
+	 * driver for LPx memory configurations. In order to avoid adding new
+	 * structures, set half_populated to true. This has the same effect as
+	 * having single channel with 64-bit width.
+	*/
+	/* GPIO_MEM_CH_SEL GPP_E13 */
+	return gpio_get(GPP_E13);
+}
+
+void variant_get_spd_info(struct mem_spd *spd_info)
+{
+	spd_info->topo = MEM_TOPO_MEMORY_DOWN;
+	spd_info->cbfs_index = variant_memory_sku();
+}