new from yh lu
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1136 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Ronald G. Minnich
parent
1621e9303c
commit
3ff7bdaad7
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@ -21,10 +21,11 @@ register "fixup_vga" = "1"
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driver mainboard.o
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driver lsi_scsi.o
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#driver adaptec_scsi.o
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driver adaptec_scsi.o
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driver promise_sata.o
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#driver intel_nic.o
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object static_devices.o
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driver intel_nic.o
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object reset.o
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#object static_devices.o
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if HAVE_MP_TABLE object mptable.o end
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if HAVE_PIRQ_TABLE object irq_tables.o end
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#
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@ -135,12 +136,46 @@ mainboardinit cpu/k8/disable_mmx_sse.inc
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###
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### Include the secondary Configuration files
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###
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northbridge amd/amdk8
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northbridge amd/amdk8 "mc0"
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pci 0:18.0
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pci 0:18.0
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pci 0:18.0
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pci 0:18.1
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pci 0:18.2
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pci 0:18.3
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southbridge amd/amd8131 "amd8131"
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pci 0:0.0
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pci 0:0.1
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pci 0:1.0
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pci 0:1.1
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end
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southbridge amd/amd8111 "amd8111"
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pci 0:0.0
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pci 0:1.0
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pci 0:1.1
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pci 0:1.2
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pci 0:1.3
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pci 0:1.5
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pci 0:1.6
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end
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end
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southbridge amd/amd8111 "amd8111"
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end
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southbridge amd/amd8131 "amd8131"
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northbridge amd/amdk8 "mc1"
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pci 0:19.0
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pci 0:19.0
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pci 0:19.0
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pci 0:19.1
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pci 0:19.2
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pci 0:19.3
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end
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#northbridge amd/amdk8
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#end
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#southbridge amd/amd8111 "amd8111"
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#end
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#southbridge amd/amd8131 "amd8131"
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#end
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#mainboardinit archi386/smp/secondary.inc
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#superio NSC/pc87360
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# register "com1" = "{1}"
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@ -149,9 +184,9 @@ end
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dir /pc80
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##dir /src/superio/winbond/w83627hf
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dir /bioscall
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dir /cpu/k8
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#dir /cpu/k8
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cpu k8 "cpu0"
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register "up" = "{.chip = &amd8131, .ht_width=8, .ht_speed=200}"
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register "up" = "{.chip = &amd8131, .ht_width=16, .ht_speed=600}"
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end
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cpu k8 "cpu1"
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@ -16,20 +16,24 @@
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#include "northbridge/amd/amdk8/reset_test.c"
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#include "debug.c"
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#define REV_B_RESET 0
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static void memreset_setup(void)
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{
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/* Set the memreset low */
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// outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
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/* Ensure the BIOS has control of the memory lines */
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// outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
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#if REV_B_RESET==1
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outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0
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#else
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outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1
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#endif
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outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
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}
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static void memreset(int controllers, const struct mem_controller *ctrl)
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{
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udelay(800);
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/* Set memreset_high */
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// outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
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udelay(90);
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udelay(800);
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#if REV_B_RESET==1
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outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
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#endif
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udelay(90);
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}
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static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
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@ -128,10 +132,6 @@ static void stop_this_cpu(void)
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#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
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static void main(void)
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{
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/*
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* GPIO28 of 8111 will control H0_MEMRESET_L
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* GPIO29 of 8111 will control H1_MEMRESET_L
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*/
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static const struct mem_controller cpu[] = {
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#if FIRST_CPU
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{
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@ -182,7 +182,7 @@ static void main(void)
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memreset_setup();
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sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
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#if 1
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#if 0
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dump_pci_devices();
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#endif
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#if 0
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@ -11,27 +11,27 @@ const struct irq_routing_table intel_irq_routing_table = {
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PIRQ_SIGNATURE, /* u32 signature */
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PIRQ_VERSION, /* u16 version */
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32+16*13, /* there can be total 13 devices on the bus */
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0, /* Where the interrupt router lies (bus) */
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1, /* Where the interrupt router lies (bus) */
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0x3b, /* Where the interrupt router lies (dev) */
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0, /* IRQs devoted exclusively to PCI usage */
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0x1022, /* Vendor */
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0x746b, /* Device */
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0, /* Crap (miniport) */
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{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
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0x37, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
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0x2b, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
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{
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{0,0x38, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0, 0},
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{0x3,0, {{0, 0}, {0, 0}, {0, 0}, {0x4, 0xdef8}}, 0, 0},
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{0x2,0x18, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0x1, 0},
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{0x2,0x30, {{0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}}, 0x2, 0},
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{0x1,0x40, {{0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}}, 0x3, 0},
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{0x1,0x38, {{0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}}, 0x4, 0},
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{0x3,0x30, {{0x3, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0},
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{0x3,0x20, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0x5, 0},
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{0x1,0x48, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0, 0}, {0, 0}}, 0, 0},
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{0x1,0x50, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0, 0}, {0, 0}}, 0, 0},
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{0x3,0x28, {{0x2, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0},
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{0x2,0x20, {{0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}}, 0x6, 0},
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{0x2,0x28, {{0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}}, 0x7, 0},
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{0x4,0, {{0, 0}, {0, 0}, {0, 0}, {0x4, 0xdef8}}, 0, 0},
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{0x3,0x18, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0x1, 0},
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{0x3,0x30, {{0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}}, 0x2, 0},
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{0x2,0x40, {{0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}}, 0x3, 0},
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{0x2,0x38, {{0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}}, 0x4, 0},
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{0x4,0x30, {{0x3, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0},
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{0x4,0x20, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0x5, 0},
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{0x2,0x48, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0, 0}, {0, 0}}, 0, 0},
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{0x2,0x50, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0, 0}, {0, 0}}, 0, 0},
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{0x4,0x28, {{0x2, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0},
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{0x3,0x20, {{0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}}, 0x6, 0},
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{0x3,0x28, {{0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}}, 0x7, 0},
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}
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};
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@ -4,6 +4,7 @@
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <device/pci_ops.h>
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#include "../../../northbridge/amd/amdk8/northbridge.h"
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#include "chip.h"
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//#include <part/mainboard.h>
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//#include "lsi_scsi.c"
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@ -46,7 +47,7 @@ static void print_pci_regs(struct device *dev)
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for(i=0;i<256;i++) {
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byte = pci_read_config8(dev, i);
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if((i%16)==0) printk_info("\n%02x:",i);
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if((i%16)==0) printk_debug("\n%02x:",i);
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printk_debug(" %02x",byte);
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}
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printk_debug("\n");
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@ -89,10 +90,11 @@ static void amd8111_enable_rom(void)
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#endif
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static void onboard_scsi_fixup(void)
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{
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struct device *dev;
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struct device *dev;
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#if 0
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unsigned char i,j,k;
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#if 1
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for(i=0;i<=4;i++) {
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for(i=0;i<=6;i++) {
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for(j=0;j<=0x1f;j++) {
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for (k=0;k<=6;k++){
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dev = dev_find_slot(i, PCI_DEVFN(j, k));
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@ -118,7 +120,7 @@ static void onboard_scsi_fixup(void)
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// print_mem();
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// amd8111_enable_rom();
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}
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/*
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#if 1
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static void vga_fixup(void) {
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// we do this right here because:
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// - all the hardware is working, and some VGA bioses seem to need
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@ -135,7 +137,7 @@ static void vga_fixup(void) {
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#endif
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}
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*/
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#endif
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static void
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enable(struct chip *chip, enum chip_pass pass)
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@ -152,8 +154,8 @@ enable(struct chip *chip, enum chip_pass pass)
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case CONF_PASS_PRE_BOOT:
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if (conf->fixup_scsi)
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onboard_scsi_fixup();
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// if (conf->fixup_vga)
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// vga_fixup();
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if (conf->fixup_vga)
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vga_fixup();
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printk_debug("mainboard fixup pass %d done\r\n",
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pass);
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break;
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@ -166,9 +168,29 @@ void final_mainboard_fixup(void)
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enable_ide_devices();
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#endif
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}
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struct chip_control mainboard_tyan_s2880_control = {
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.enable= enable,
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.name= "Tyan s2880 mainboard "
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static struct device_operations mainboard_operations = {
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.read_resources = root_dev_read_resources,
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.set_resources = root_dev_set_resources,
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.enable_resources = enable_childrens_resources,
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.init = 0,
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.scan_bus = amdk8_scan_root_bus,
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.enable = 0,
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};
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static void enumerate(struct chip *chip)
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{
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struct chip *child;
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dev_root.ops = &mainboard_operations;
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chip->dev = &dev_root;
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chip->bus = 0;
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for(child = chip->children; child; child = child->next) {
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child->bus = &dev_root.link[0];
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}
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}
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struct chip_control mainboard_tyan_s2880_control = {
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.enable = enable,
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.enumerate = enumerate,
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.name = "Tyan s2880 mainboard ",
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};
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@ -36,19 +36,21 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
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smp_write_bus(mc, 1, "PCI ");
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smp_write_bus(mc, 2, "PCI ");
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smp_write_bus(mc, 3, "PCI ");
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smp_write_bus(mc, 4, "ISA ");
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smp_write_bus(mc, 4, "PCI ");
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smp_write_bus(mc, 5, "ISA ");
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/*I/O APICs: APIC ID Version State Address*/
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smp_write_ioapic(mc, 2, 0x11, 0xfec00000);
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{
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struct pci_dev *dev;
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uint32_t base;
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dev = dev_find_slot(0, PCI_DEVFN(0x1,1));
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dev = dev_find_slot(1, PCI_DEVFN(0x1,1));
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if (dev) {
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base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
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base &= PCI_BASE_ADDRESS_MEM_MASK;
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smp_write_ioapic(mc, 3, 0x11, base);
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}
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dev = dev_find_slot(0, PCI_DEVFN(0x2,1));
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dev = dev_find_slot(1, PCI_DEVFN(0x2,1));
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if (dev) {
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base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
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base &= PCI_BASE_ADDRESS_MEM_MASK;
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@ -57,64 +59,64 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
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}
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/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#
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*/ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x4, 0x0, 0x2, 0x0);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x4, 0x1, 0x2, 0x1);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x4, 0x0, 0x2, 0x2);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x4, 0x3, 0x2, 0x3);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x4, 0x4, 0x2, 0x4);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x4, 0x6, 0x2, 0x6);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x4, 0x7, 0x2, 0x7);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x4, 0x8, 0x2, 0x8);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x4, 0xc, 0x2, 0xc);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x4, 0xd, 0x2, 0xd);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x4, 0xe, 0x2, 0xe);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x4, 0xf, 0x2, 0xf);
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*/ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x5, 0x0, 0x2, 0x0);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x5, 0x1, 0x2, 0x1);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x5, 0x0, 0x2, 0x2);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x5, 0x3, 0x2, 0x3);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x5, 0x4, 0x2, 0x4);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x5, 0x6, 0x2, 0x6);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x5, 0x7, 0x2, 0x7);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x5, 0x8, 0x2, 0x8);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x5, 0xc, 0x2, 0xc);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x5, 0xd, 0x2, 0xd);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x5, 0xe, 0x2, 0xe);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x5, 0xf, 0x2, 0xf);
|
||||
|
||||
|
||||
//On Board AMD USB
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, 0x3, 0x2, 0x13);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0x3, 0x2, 0x13);
|
||||
|
||||
//On Board ATI Display Adapter
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, 0x18, 0x2, 0x12);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0x18, 0x2, 0x12);
|
||||
|
||||
//Slot 5 PCI 32
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, 0x10, 0x2, 0x10);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, 0x11, 0x2, 0x11);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, 0x12, 0x2, 0x12); //
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, 0x13, 0x2, 0x13); //
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0x10, 0x2, 0x10);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0x11, 0x2, 0x11);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0x12, 0x2, 0x12); //
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0x13, 0x2, 0x13); //
|
||||
|
||||
//On Board Promise Serial ATA
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, 0x14, 0x2, 0x11);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0x14, 0x2, 0x11);
|
||||
|
||||
//Slot 3 PCIX 100/66
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x20, 0x3, 0x3);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x21, 0x3, 0x0);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x22, 0x3, 0x1);//
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x23, 0x3, 0x2);//
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x20, 0x3, 0x3);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x21, 0x3, 0x0);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x22, 0x3, 0x1);//
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x23, 0x3, 0x2);//
|
||||
|
||||
//Slot 4 PCIX 100/66
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x1c, 0x3, 0x2);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x1d, 0x3, 0x3);//
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x1e, 0x3, 0x0);//
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x1f, 0x3, 0x1);//
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x1c, 0x3, 0x2);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x1d, 0x3, 0x3);//
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x1e, 0x3, 0x0);//
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x1f, 0x3, 0x1);//
|
||||
|
||||
//On Board NIC and LSI scsi
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x24, 0x3, 0x0);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x25, 0x3, 0x1);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x28, 0x3, 0x0);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x29, 0x3, 0x1);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x24, 0x3, 0x0);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x25, 0x3, 0x1);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x28, 0x3, 0x0);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x29, 0x3, 0x1);
|
||||
|
||||
//Slot 1 PCI-X 133/100/66
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0xc, 0x4, 0x0);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0xd, 0x4, 0x1);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0xe, 0x4, 0x2); //
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0xf, 0x4, 0x3); //
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, 0xc, 0x4, 0x0);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, 0xd, 0x4, 0x1);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, 0xe, 0x4, 0x2); //
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, 0xf, 0x4, 0x3); //
|
||||
|
||||
//Slot 2 PCI-X 133/100/66
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x18, 0x4, 0x1);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x19, 0x4, 0x2);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x1a, 0x4, 0x3);//
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x1b, 0x4, 0x0);//
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, 0x18, 0x4, 0x1);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, 0x19, 0x4, 0x2);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, 0x1a, 0x4, 0x3);//
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, 0x1b, 0x4, 0x0);//
|
||||
|
||||
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
|
||||
smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x0, 0x0, MP_APIC_ALL, 0x0);
|
||||
|
|
|
|||
|
|
@ -21,9 +21,10 @@ register "fixup_vga" = "1"
|
|||
|
||||
driver mainboard.o
|
||||
driver adaptec_scsi.o
|
||||
#driver si_sata.o
|
||||
#driver intel_nic.o
|
||||
object static_devices.o
|
||||
driver si_sata.o
|
||||
driver intel_nic.o
|
||||
object reset.o
|
||||
#object static_devices.o
|
||||
if HAVE_MP_TABLE object mptable.o end
|
||||
if HAVE_PIRQ_TABLE object irq_tables.o end
|
||||
#
|
||||
|
|
@ -134,12 +135,45 @@ mainboardinit cpu/k8/disable_mmx_sse.inc
|
|||
###
|
||||
### Include the secondary Configuration files
|
||||
###
|
||||
northbridge amd/amdk8
|
||||
northbridge amd/amdk8 "mc0"
|
||||
pci 0:18.0
|
||||
pci 0:18.0
|
||||
pci 0:18.0
|
||||
pci 0:18.1
|
||||
pci 0:18.2
|
||||
pci 0:18.3
|
||||
southbridge amd/amd8131 "amd8131"
|
||||
pci 0:0.0
|
||||
pci 0:0.1
|
||||
pci 0:1.0
|
||||
pci 0:1.1
|
||||
end
|
||||
southbridge amd/amd8111 "amd8111"
|
||||
pci 0:0.0
|
||||
pci 0:1.0
|
||||
pci 0:1.1
|
||||
pci 0:1.2
|
||||
pci 0:1.3
|
||||
pci 0:1.5
|
||||
pci 0:1.6
|
||||
end
|
||||
end
|
||||
southbridge amd/amd8111 "amd8111"
|
||||
end
|
||||
southbridge amd/amd8131 "amd8131"
|
||||
|
||||
northbridge amd/amdk8 "mc1"
|
||||
pci 0:19.0
|
||||
pci 0:19.0
|
||||
pci 0:19.0
|
||||
pci 0:19.1
|
||||
pci 0:19.2
|
||||
pci 0:19.3
|
||||
end
|
||||
|
||||
#northbridge amd/amdk8
|
||||
#end
|
||||
#southbridge amd/amd8111 "amd8111"
|
||||
#end
|
||||
#southbridge amd/amd8131 "amd8131"
|
||||
#end
|
||||
#mainboardinit archi386/smp/secondary.inc
|
||||
#superio NSC/pc87360
|
||||
# register "com1" = "{1}"
|
||||
|
|
@ -148,9 +182,9 @@ end
|
|||
dir /pc80
|
||||
##dir /src/superio/winbond/w83627hf
|
||||
dir /bioscall
|
||||
dir /cpu/k8
|
||||
#dir /cpu/k8
|
||||
cpu k8 "cpu0"
|
||||
register "up" = "{.chip = &amd8131, .ht_width=8, .ht_speed=200}"
|
||||
register "up" = "{.chip = &amd8131, .ht_width=16, .ht_speed=600}"
|
||||
end
|
||||
|
||||
cpu k8 "cpu1"
|
||||
|
|
|
|||
|
|
@ -11,7 +11,7 @@ const struct irq_routing_table intel_irq_routing_table = {
|
|||
PIRQ_SIGNATURE, /* u32 signature */
|
||||
PIRQ_VERSION, /* u16 version */
|
||||
32+16*15, /* there can be total 15 devices on the bus */
|
||||
0, /* Where the interrupt router lies (bus) */
|
||||
1, /* Where the interrupt router lies (bus) */
|
||||
0x3b, /* Where the interrupt router lies (dev) */
|
||||
0, /* IRQs devoted exclusively to PCI usage */
|
||||
0x1022, /* Vendor */
|
||||
|
|
@ -21,19 +21,19 @@ const struct irq_routing_table intel_irq_routing_table = {
|
|||
0x8d, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
|
||||
{
|
||||
{0,0x38, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0, 0},
|
||||
{0x3,0, {{0, 0}, {0, 0}, {0, 0}, {0x4, 0xdef8}}, 0, 0},
|
||||
{0x3,0x30, {{0x3, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0},
|
||||
{0x2,0x18, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0x1, 0},
|
||||
{0x2,0x8, {{0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}}, 0x2, 0},
|
||||
{0x1,0x18, {{0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}}, 0x3, 0},
|
||||
{0x1,0x10, {{0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}}, 0x4, 0},
|
||||
{0x3,0x20, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0x5, 0},
|
||||
{0x3,0x28, {{0x4, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0},
|
||||
{0x3,0x40, {{0x3, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0},
|
||||
{0x1,0x30, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0, 0}, {0, 0}}, 0, 0},
|
||||
{0x2,0x20, {{0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}}, 0x6, 0},
|
||||
{0x2,0x28, {{0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}}, 0x7, 0},
|
||||
{0x1,0x28, {{0x3, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0},
|
||||
{0x1,0x48, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0, 0}, {0, 0}}, 0, 0},
|
||||
{0x4,0, {{0, 0}, {0, 0}, {0, 0}, {0x4, 0xdef8}}, 0, 0},
|
||||
{0x4,0x30, {{0x3, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0},
|
||||
{0x3,0x18, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0x1, 0},
|
||||
{0x3,0x8, {{0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}}, 0x2, 0},
|
||||
{0x2,0x18, {{0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}}, 0x3, 0},
|
||||
{0x2,0x10, {{0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}}, 0x4, 0},
|
||||
{0x4,0x20, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0x5, 0},
|
||||
{0x4,0x28, {{0x4, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0},
|
||||
{0x4,0x40, {{0x3, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0},
|
||||
{0x2,0x30, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0, 0}, {0, 0}}, 0, 0},
|
||||
{0x3,0x20, {{0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}}, 0x6, 0},
|
||||
{0x3,0x28, {{0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}}, 0x7, 0},
|
||||
{0x2,0x28, {{0x3, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0},
|
||||
{0x2,0x48, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0, 0}, {0, 0}}, 0, 0},
|
||||
}
|
||||
};
|
||||
|
|
|
|||
|
|
@ -4,6 +4,7 @@
|
|||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <device/pci_ops.h>
|
||||
#include "../../../northbridge/amd/amdk8/northbridge.h"
|
||||
#include "chip.h"
|
||||
//#include <part/mainboard.h>
|
||||
//#include "lsi_scsi.c"
|
||||
|
|
@ -91,7 +92,7 @@ static void onboard_scsi_fixup(void)
|
|||
{
|
||||
struct device *dev;
|
||||
unsigned char i,j,k;
|
||||
#if 1
|
||||
#if 0
|
||||
for(i=0;i<=4;i++) {
|
||||
for(j=0;j<=0x1f;j++) {
|
||||
for (k=0;k<=6;k++){
|
||||
|
|
@ -166,9 +167,28 @@ void final_mainboard_fixup(void)
|
|||
enable_ide_devices();
|
||||
#endif
|
||||
}
|
||||
|
||||
struct chip_control mainboard_tyan_s2882_control = {
|
||||
.enable= enable,
|
||||
.name= "Tyan s2882 mainboard "
|
||||
static struct device_operations mainboard_operations = {
|
||||
.read_resources = root_dev_read_resources,
|
||||
.set_resources = root_dev_set_resources,
|
||||
.enable_resources = enable_childrens_resources,
|
||||
.init = 0,
|
||||
.scan_bus = amdk8_scan_root_bus,
|
||||
.enable = 0,
|
||||
};
|
||||
|
||||
static void enumerate(struct chip *chip)
|
||||
{
|
||||
struct chip *child;
|
||||
dev_root.ops = &mainboard_operations;
|
||||
chip->dev = &dev_root;
|
||||
chip->bus = 0;
|
||||
for(child = chip->children; child; child = child->next) {
|
||||
child->bus = &dev_root.link[0];
|
||||
}
|
||||
}
|
||||
struct chip_control mainboard_tyan_s2882_control = {
|
||||
.enable = enable,
|
||||
.enumerate = enumerate,
|
||||
.name = "Tyan s2882 mainboard ",
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -36,19 +36,20 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
|
|||
smp_write_bus(mc, 1, "PCI ");
|
||||
smp_write_bus(mc, 2, "PCI ");
|
||||
smp_write_bus(mc, 3, "PCI ");
|
||||
smp_write_bus(mc, 4, "ISA ");
|
||||
smp_write_bus(mc, 4, "PCI ");
|
||||
smp_write_bus(mc, 5, "ISA ");
|
||||
/*I/O APICs: APIC ID Version State Address*/
|
||||
smp_write_ioapic(mc, 2, 0x11, 0xfec00000);
|
||||
{
|
||||
struct pci_dev *dev;
|
||||
uint32_t base;
|
||||
dev = dev_find_slot(0, PCI_DEVFN(0x1,1));
|
||||
dev = dev_find_slot(1, PCI_DEVFN(0x1,1));
|
||||
if (dev) {
|
||||
base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
|
||||
base &= PCI_BASE_ADDRESS_MEM_MASK;
|
||||
smp_write_ioapic(mc, 3, 0x11, base);
|
||||
}
|
||||
dev = dev_find_slot(0, PCI_DEVFN(0x2,1));
|
||||
dev = dev_find_slot(1, PCI_DEVFN(0x2,1));
|
||||
if (dev) {
|
||||
base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
|
||||
base &= PCI_BASE_ADDRESS_MEM_MASK;
|
||||
|
|
@ -57,67 +58,67 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
|
|||
}
|
||||
|
||||
/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#
|
||||
*/ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x4, 0x0, 0x2, 0x0);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x4, 0x1, 0x2, 0x1);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x4, 0x0, 0x2, 0x2);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x4, 0x3, 0x2, 0x3);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x4, 0x4, 0x2, 0x4);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x4, 0x6, 0x2, 0x6);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x4, 0x7, 0x2, 0x7);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x4, 0x8, 0x2, 0x8);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x4, 0xc, 0x2, 0xc);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x4, 0xd, 0x2, 0xd);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x4, 0xe, 0x2, 0xe);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x4, 0xf, 0x2, 0xf);
|
||||
*/ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x5, 0x0, 0x2, 0x0);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x5, 0x1, 0x2, 0x1);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x5, 0x0, 0x2, 0x2);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x5, 0x3, 0x2, 0x3);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x5, 0x4, 0x2, 0x4);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x5, 0x6, 0x2, 0x6);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x5, 0x7, 0x2, 0x7);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x5, 0x8, 0x2, 0x8);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x5, 0xc, 0x2, 0xc);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x5, 0xd, 0x2, 0xd);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x5, 0xe, 0x2, 0xe);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x5, 0xf, 0x2, 0xf);
|
||||
|
||||
//??? smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x1f, 0x2, 0x13);
|
||||
|
||||
|
||||
//On Board AMD USB
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, 0x3, 0x2, 0x13);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0x3, 0x2, 0x13);
|
||||
|
||||
//On Board ATI Display Adapter
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, 0x18, 0x2, 0x12);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0x18, 0x2, 0x12);
|
||||
#if 0
|
||||
//Slot 5 PCI 32
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, 0x10, 0x2, 0x10);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, 0x11, 0x2, 0x11);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, 0x12, 0x2, 0x12); //
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, 0x13, 0x2, 0x13); //
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0x10, 0x2, 0x10);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0x11, 0x2, 0x11);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0x12, 0x2, 0x12); //
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0x13, 0x2, 0x13); //
|
||||
#endif
|
||||
//Onboard SI Serial ATA
|
||||
// smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, 0x14, 0x2, 0x11);
|
||||
// smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0x14, 0x2, 0x11);
|
||||
#if 0
|
||||
//Slot 3 PCIX 100/66
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x20, 0x3, 0x3);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x21, 0x3, 0x0);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x22, 0x3, 0x1);//
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x23, 0x3, 0x2);//
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x20, 0x3, 0x3);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x21, 0x3, 0x0);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x22, 0x3, 0x1);//
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x23, 0x3, 0x2);//
|
||||
|
||||
//Slot 4 PCIX 100/66
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x1c, 0x3, 0x2);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x1d, 0x3, 0x3);//
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x1e, 0x3, 0x0);//
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x1f, 0x3, 0x1);//
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x1c, 0x3, 0x2);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x1d, 0x3, 0x3);//
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x1e, 0x3, 0x0);//
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x1f, 0x3, 0x1);//
|
||||
#endif
|
||||
//Onboard adaptec scsi
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x18, 0x3, 0x0);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x19, 0x3, 0x1);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x18, 0x3, 0x0);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x19, 0x3, 0x1);
|
||||
//On Board NIC
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x24, 0x3, 0x0);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x25, 0x3, 0x1);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x24, 0x3, 0x0);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x25, 0x3, 0x1);
|
||||
#if 0
|
||||
//Slot 1 PCI-X 133/100/66
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0xc, 0x4, 0x0);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0xd, 0x4, 0x1);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0xe, 0x4, 0x2); //
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0xf, 0x4, 0x3); //
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, 0xc, 0x4, 0x0);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, 0xd, 0x4, 0x1);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, 0xe, 0x4, 0x2); //
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, 0xf, 0x4, 0x3); //
|
||||
|
||||
//Slot 2 PCI-X 133/100/66
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x18, 0x4, 0x1);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x19, 0x4, 0x2);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x1a, 0x4, 0x3);//
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x1b, 0x4, 0x0);//
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, 0x18, 0x4, 0x1);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, 0x19, 0x4, 0x2);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, 0x1a, 0x4, 0x3);//
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, 0x1b, 0x4, 0x0);//
|
||||
#endif
|
||||
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
|
||||
smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x0, 0x0, MP_APIC_ALL, 0x0);
|
||||
|
|
|
|||
|
|
@ -24,7 +24,8 @@ driver ti_firewire.o
|
|||
driver adaptec_scsi.o
|
||||
driver si_sata.o
|
||||
driver intel_nic.o
|
||||
object static_devices.o
|
||||
#object static_devices.o
|
||||
object reset.o
|
||||
if HAVE_MP_TABLE object mptable.o end
|
||||
if HAVE_PIRQ_TABLE object irq_tables.o end
|
||||
#
|
||||
|
|
@ -135,14 +136,52 @@ mainboardinit cpu/k8/disable_mmx_sse.inc
|
|||
###
|
||||
### Include the secondary Configuration files
|
||||
###
|
||||
northbridge amd/amdk8
|
||||
northbridge amd/amdk8 "mc0"
|
||||
pci 0:18.0
|
||||
pci 0:18.0
|
||||
pci 0:18.0
|
||||
pci 0:18.1
|
||||
pci 0:18.2
|
||||
pci 0:18.3
|
||||
southbridge amd/amd8131 "amd8131"
|
||||
pci 0:0.0
|
||||
pci 0:0.1
|
||||
pci 0:1.0
|
||||
pci 0:1.1
|
||||
end
|
||||
southbridge amd/amd8111 "amd8111"
|
||||
pci 0:0.0
|
||||
pci 0:1.0
|
||||
pci 0:1.1
|
||||
pci 0:1.2
|
||||
pci 0:1.3
|
||||
pci 0:1.5
|
||||
pci 0:1.6
|
||||
end
|
||||
southbridge amd/amd8151 "amd8151"
|
||||
pci 2:0.0
|
||||
pci 2:1.0
|
||||
end
|
||||
end
|
||||
southbridge amd/amd8111 "amd8111"
|
||||
end
|
||||
southbridge amd/amd8131 "amd8131"
|
||||
end
|
||||
southbridge amd/amd8151 "amd8151"
|
||||
|
||||
northbridge amd/amdk8 "mc1"
|
||||
pci 0:19.0
|
||||
pci 0:19.0
|
||||
pci 0:19.0
|
||||
pci 0:19.1
|
||||
pci 0:19.2
|
||||
pci 0:19.3
|
||||
end
|
||||
|
||||
#northbridge amd/amdk8
|
||||
#end
|
||||
#southbridge amd/amd8111 "amd8111"
|
||||
#end
|
||||
#southbridge amd/amd8131 "amd8131"
|
||||
#end
|
||||
#southbridge amd/amd8151 "amd8151"
|
||||
#end
|
||||
|
||||
#mainboardinit archi386/smp/secondary.inc
|
||||
#superio NSC/pc87360
|
||||
# register "com1" = "{1}"
|
||||
|
|
@ -150,7 +189,8 @@ end
|
|||
#end
|
||||
dir /pc80
|
||||
##dir /src/superio/winbond/w83627hf
|
||||
dir /cpu/k8
|
||||
dir /bioscall
|
||||
#dir /cpu/k8
|
||||
cpu k8 "cpu0"
|
||||
register "up" = "{.chip = &amd8151, .ht_width=16, .ht_speed=600}"
|
||||
register "down" = "{.chip = &amd8131, .ht_width=16, .ht_speed=600}"
|
||||
|
|
|
|||
|
|
@ -1,4 +1,5 @@
|
|||
#define ASSEMBLY 1
|
||||
|
||||
#include <stdint.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <cpu/p6/apic.h>
|
||||
|
|
@ -16,20 +17,24 @@
|
|||
#include "northbridge/amd/amdk8/reset_test.c"
|
||||
#include "debug.c"
|
||||
|
||||
#define REV_B_RESET 0
|
||||
static void memreset_setup(void)
|
||||
{
|
||||
/* Set the memreset low */
|
||||
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); // BY LYH 28->16 0<<0 --> 1<<0
|
||||
/* Ensure the BIOS has control of the memory lines */
|
||||
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17); // BY LYH 29->17
|
||||
#if REV_B_RESET==1
|
||||
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0
|
||||
#else
|
||||
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1
|
||||
#endif
|
||||
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
|
||||
}
|
||||
|
||||
static void memreset(int controllers, const struct mem_controller *ctrl)
|
||||
{
|
||||
udelay(800);
|
||||
/* Set memreset_high */
|
||||
// outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); // BY LYH 28->17
|
||||
udelay(90);
|
||||
udelay(800);
|
||||
#if REV_B_RESET==1
|
||||
outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
|
||||
#endif
|
||||
udelay(90);
|
||||
}
|
||||
|
||||
static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
|
||||
|
|
@ -130,10 +135,6 @@ static void stop_this_cpu(void)
|
|||
#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
|
||||
static void main(void)
|
||||
{
|
||||
/*
|
||||
* GPIO28 of 8111 will control H0_MEMRESET_L
|
||||
* GPIO29 of 8111 will control H1_MEMRESET_L
|
||||
*/
|
||||
static const struct mem_controller cpu[] = {
|
||||
#if FIRST_CPU
|
||||
{
|
||||
|
|
@ -172,8 +173,6 @@ static void main(void)
|
|||
setup_s2885_resource_map();
|
||||
setup_coherent_ht_domain();
|
||||
enumerate_ht_chain(0);
|
||||
//setup_resource_map_x();
|
||||
//enumerate_ht_chain(0);
|
||||
distinguish_cpu_resets(0);
|
||||
|
||||
#if 0
|
||||
|
|
@ -186,7 +185,7 @@ static void main(void)
|
|||
memreset_setup();
|
||||
sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
|
||||
|
||||
#if 1
|
||||
#if 0
|
||||
dump_pci_devices();
|
||||
#endif
|
||||
#if 0
|
||||
|
|
|
|||
|
|
@ -11,7 +11,7 @@ const struct irq_routing_table intel_irq_routing_table = {
|
|||
PIRQ_SIGNATURE, /* u32 signature */
|
||||
PIRQ_VERSION, /* u16 version */
|
||||
32+16*11, /* there can be total 11 devices on the bus */
|
||||
0, /* Where the interrupt router lies (bus) */
|
||||
1, /* Where the interrupt router lies (bus) */
|
||||
0x3b, /* Where the interrupt router lies (dev) */
|
||||
0, /* IRQs devoted exclusively to PCI usage */
|
||||
0x1022, /* Vendor */
|
||||
|
|
@ -21,15 +21,15 @@ const struct irq_routing_table intel_irq_routing_table = {
|
|||
0x35, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
|
||||
{
|
||||
{0,0x38, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0, 0},
|
||||
{0x3,0, {{0, 0}, {0, 0}, {0, 0}, {0x4, 0xdef8}}, 0, 0},
|
||||
{0x5,0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0, 0}, {0, 0}}, 0x6, 0},
|
||||
{0x2,0x18, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0x1, 0},
|
||||
{0x2,0x30, {{0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}}, 0x2, 0},
|
||||
{0x1,0x40, {{0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}}, 0x3, 0},
|
||||
{0x1,0x38, {{0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}}, 0x4, 0},
|
||||
{0x3,0x50, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0x5, 0},
|
||||
{0x1,0x48, {{0x1, 0xdef8}, {2, 0xdef8}, {0, 0}, {0, 0}}, 0, 0},
|
||||
{0x3,0x58, {{0x2, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0},
|
||||
{0x3,0x60, {{0x4, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0},
|
||||
{0x4,0, {{0, 0}, {0, 0}, {0, 0}, {0x4, 0xdef8}}, 0, 0},
|
||||
{0x6,0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0, 0}, {0, 0}}, 0x6, 0},
|
||||
{0x3,0x18, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0x1, 0},
|
||||
{0x3,0x30, {{0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}}, 0x2, 0},
|
||||
{0x2,0x40, {{0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}}, 0x3, 0},
|
||||
{0x2,0x38, {{0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}}, 0x4, 0},
|
||||
{0x4,0x50, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0x5, 0},
|
||||
{0x2,0x48, {{0x1, 0xdef8}, {2, 0xdef8}, {0, 0}, {0, 0}}, 0, 0},
|
||||
{0x4,0x58, {{0x2, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0},
|
||||
{0x4,0x60, {{0x4, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0},
|
||||
}
|
||||
};
|
||||
|
|
|
|||
|
|
@ -4,9 +4,9 @@
|
|||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <device/pci_ops.h>
|
||||
#include "../../../northbridge/amd/amdk8/northbridge.h"
|
||||
#include "chip.h"
|
||||
//#include <part/mainboard.h>
|
||||
//#include "lsi_scsi.c"
|
||||
unsigned long initial_apicid[CONFIG_MAX_CPUS] =
|
||||
{
|
||||
0,1
|
||||
|
|
@ -46,7 +46,7 @@ static void print_pci_regs(struct device *dev)
|
|||
for(i=0;i<256;i++) {
|
||||
byte = pci_read_config8(dev, i);
|
||||
|
||||
if((i%16)==0) printk_info("\n%02x:",i);
|
||||
if((i%16)==0) printk_debug("\n%02x:",i);
|
||||
printk_debug(" %02x",byte);
|
||||
}
|
||||
printk_debug("\n");
|
||||
|
|
@ -89,10 +89,11 @@ static void amd8111_enable_rom(void)
|
|||
#endif
|
||||
static void onboard_scsi_fixup(void)
|
||||
{
|
||||
struct device *dev;
|
||||
struct device *dev;
|
||||
#if 0
|
||||
unsigned char i,j,k;
|
||||
#if 1
|
||||
for(i=0;i<=4;i++) {
|
||||
|
||||
for(i=0;i<=6;i++) {
|
||||
for(j=0;j<=0x1f;j++) {
|
||||
for (k=0;k<=6;k++){
|
||||
dev = dev_find_slot(i, PCI_DEVFN(j, k));
|
||||
|
|
@ -118,7 +119,7 @@ static void onboard_scsi_fixup(void)
|
|||
// print_mem();
|
||||
// amd8111_enable_rom();
|
||||
}
|
||||
/*
|
||||
|
||||
static void vga_fixup(void) {
|
||||
// we do this right here because:
|
||||
// - all the hardware is working, and some VGA bioses seem to need
|
||||
|
|
@ -130,12 +131,12 @@ static void vga_fixup(void) {
|
|||
#endif
|
||||
#if CONFIG_VGABIOS == 1
|
||||
printk_debug("DO THE VGA BIOS\n");
|
||||
do_vgabios();
|
||||
do_vgabios(0x0600);
|
||||
post_code(0x93);
|
||||
#endif
|
||||
|
||||
}
|
||||
*/
|
||||
|
||||
|
||||
static void
|
||||
enable(struct chip *chip, enum chip_pass pass)
|
||||
|
|
@ -152,8 +153,8 @@ enable(struct chip *chip, enum chip_pass pass)
|
|||
case CONF_PASS_PRE_BOOT:
|
||||
if (conf->fixup_scsi)
|
||||
onboard_scsi_fixup();
|
||||
// if (conf->fixup_vga)
|
||||
// vga_fixup();
|
||||
if (conf->fixup_vga)
|
||||
vga_fixup();
|
||||
printk_debug("mainboard fixup pass %d done\r\n",
|
||||
pass);
|
||||
break;
|
||||
|
|
@ -166,9 +167,27 @@ void final_mainboard_fixup(void)
|
|||
enable_ide_devices();
|
||||
#endif
|
||||
}
|
||||
|
||||
struct chip_control mainboard_tyan_s2885_control = {
|
||||
.enable= enable,
|
||||
.name= "Tyan s2885 mainboard "
|
||||
static struct device_operations mainboard_operations = {
|
||||
.read_resources = root_dev_read_resources,
|
||||
.set_resources = root_dev_set_resources,
|
||||
.enable_resources = enable_childrens_resources,
|
||||
.init = 0,
|
||||
.scan_bus = amdk8_scan_root_bus,
|
||||
.enable = 0,
|
||||
};
|
||||
|
||||
static void enumerate(struct chip *chip)
|
||||
{
|
||||
struct chip *child;
|
||||
dev_root.ops = &mainboard_operations;
|
||||
chip->dev = &dev_root;
|
||||
chip->bus = 0;
|
||||
for(child = chip->children; child; child = child->next) {
|
||||
child->bus = &dev_root.link[0];
|
||||
}
|
||||
}
|
||||
struct chip_control mainboard_tyan_s2885_control = {
|
||||
.enable = enable,
|
||||
.enumerate = enumerate,
|
||||
.name = "Tyan s2885 mainboard ",
|
||||
};
|
||||
|
|
|
|||
|
|
@ -37,12 +37,13 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
|
|||
smp_write_bus(mc, 1, "PCI ");
|
||||
smp_write_bus(mc, 2, "PCI ");
|
||||
smp_write_bus(mc, 3, "PCI ");
|
||||
smp_write_bus(mc, 4, "PCI ");
|
||||
#if 1
|
||||
isa_bus = 6;
|
||||
smp_write_bus(mc, 4, "PCI "); //8151 1022/7454 1022/7455
|
||||
smp_write_bus(mc, 5, "PCI "); //Bridge
|
||||
isa_bus = 7;
|
||||
smp_write_bus(mc, 5, "PCI "); //8151 1022/7454 1022/7455
|
||||
smp_write_bus(mc, 6, "PCI "); //Bridge
|
||||
#else
|
||||
isa_bus = 4;
|
||||
isa_bus = 5;
|
||||
#endif
|
||||
smp_write_bus(mc, isa_bus, "ISA ");
|
||||
/*I/O APICs: APIC ID Version State Address*/
|
||||
|
|
@ -50,13 +51,13 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
|
|||
{
|
||||
struct pci_dev *dev;
|
||||
uint32_t base;
|
||||
dev = dev_find_slot(0, PCI_DEVFN(0x1,1));
|
||||
dev = dev_find_slot(1, PCI_DEVFN(0x1,1));
|
||||
if (dev) {
|
||||
base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
|
||||
base &= PCI_BASE_ADDRESS_MEM_MASK;
|
||||
smp_write_ioapic(mc, 3, 0x11, base);
|
||||
}
|
||||
dev = dev_find_slot(0, PCI_DEVFN(0x2,1));
|
||||
dev = dev_find_slot(1, PCI_DEVFN(0x2,1));
|
||||
if (dev) {
|
||||
base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
|
||||
base &= PCI_BASE_ADDRESS_MEM_MASK;
|
||||
|
|
@ -79,51 +80,51 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
|
|||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, isa_bus, 0xe, 0x2, 0xe);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, isa_bus, 0xf, 0x2, 0xf);
|
||||
//??? What
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x1f, 0x2, 0x13);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x1f, 0x2, 0x13);
|
||||
//Onboard AMD AC97 Audio
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x1d, 0x2, 0x11);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x1d, 0x2, 0x11);
|
||||
// Onboard AMD USB
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, 0x3, 0x2, 0x13);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0x3, 0x2, 0x13);
|
||||
|
||||
// AGP Display Adapter
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x0, 0x2, 0x10);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, 0x0, 0x2, 0x10);
|
||||
|
||||
// Onboard Serial ATA
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, 0x2c, 0x2, 0x11);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0x2c, 0x2, 0x11);
|
||||
//Onboard Firewire
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, 0x30, 0x2, 0x13);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0x30, 0x2, 0x13);
|
||||
//Onboard Broadcom NIC
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x24, 0x3, 0x0);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x24, 0x3, 0x0);
|
||||
|
||||
//Slot 5 PCI 32
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, 0x28, 0x2, 0x10);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, 0x29, 0x2, 0x11);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, 0x2a, 0x2, 0x12); //
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, 0x2b, 0x2, 0x13); //
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0x28, 0x2, 0x10);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0x29, 0x2, 0x11);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0x2a, 0x2, 0x12); //
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0x2b, 0x2, 0x13); //
|
||||
|
||||
//Slot 3 PCIX 100/66
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x20, 0x3, 0x3);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x21, 0x3, 0x0);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x22, 0x3, 0x1);//
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x23, 0x3, 0x2);//
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x20, 0x3, 0x3);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x21, 0x3, 0x0);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x22, 0x3, 0x1);//
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x23, 0x3, 0x2);//
|
||||
|
||||
//Slot 4 PCIX 100/66
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x1c, 0x3, 0x2);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x1d, 0x3, 0x3);//
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x1e, 0x3, 0x0);//
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x1f, 0x3, 0x1);//
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x1c, 0x3, 0x2);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x1d, 0x3, 0x3);//
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x1e, 0x3, 0x0);//
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x1f, 0x3, 0x1);//
|
||||
|
||||
//Slot 1 PCI-X 133/100/66
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0xc, 0x4, 0x0);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0xd, 0x4, 0x1);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0xe, 0x4, 0x2); //
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0xf, 0x4, 0x3); //
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, 0xc, 0x4, 0x0);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, 0xd, 0x4, 0x1);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, 0xe, 0x4, 0x2); //
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, 0xf, 0x4, 0x3); //
|
||||
|
||||
//Slot 2 PCI-X 133/100/66
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x18, 0x4, 0x1);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x19, 0x4, 0x2);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x1a, 0x4, 0x3);//
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x1b, 0x4, 0x0);//
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, 0x18, 0x4, 0x1);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, 0x19, 0x4, 0x2);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, 0x1a, 0x4, 0x3);//
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, 0x1b, 0x4, 0x0);//
|
||||
|
||||
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
|
||||
smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x0, 0x0, MP_APIC_ALL, 0x0);
|
||||
|
|
|
|||
|
|
@ -252,8 +252,8 @@ static void setup_s2885_resource_map(void)
|
|||
* [31:24] Bus Number Limit i
|
||||
* This field defines the highest bus number in configuration regin i
|
||||
*/
|
||||
PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x03000203,
|
||||
PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x05040003,
|
||||
PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x04000203,
|
||||
PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x06050003,
|
||||
PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
|
||||
};
|
||||
|
|
|
|||
Loading…
Reference in New Issue