From 3ff948651a3ff848f761e55f14a3011502f63dbd Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Sun, 4 Oct 2020 16:34:10 +0200 Subject: [PATCH] mb/asus/f2a85-m_pro: Enable super-I/O LDNs 0x0f and 0x14 The LDNs don't have a 0x30 register to enable them. However, with the devices set to `off`, coreboot won't configure them. Change-Id: Iaea37c88524904a1dae8a6d3b5f07c6ea25bc3b2 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/46021 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb b/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb index 654716b2b2..4e124f28e3 100644 --- a/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb +++ b/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb @@ -97,10 +97,10 @@ chip northbridge/amd/agesa/family15tn/root_complex end device pnp 2e.d off end # WDT1 device pnp 2e.e off end # CIR WAKE-UP - device pnp 2e.f off # GPIO Push-pull/Open-drain selection + device pnp 2e.f on # GPIO Push-pull/Open-drain selection irq 0xe6 = 7f end - device pnp 2e.14 off # PORT80 UART + device pnp 2e.14 on # PORT80 UART irq 0xe0 = 0x00 end device pnp 2e.16 off end # Deep Sleep