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arch/x86/ioapic: Add get_ioapic_id() and get_ioapic_version() 

Change-Id: I4ad080653c9af94a4dc73d93ddc4c8c117a682b9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55282
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Kyösti Mälkki 2021-06-06 08:27:15 +03:00
parent 8997e7b5ae
commit 401ec98e06
4 changed files with 16 additions and 15 deletions
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2
src/arch/x86/include/arch/ioapic.h
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@ -29,6 +29,8 @@
u32 io_apic_read(void *ioapic_base, u32 reg); u32 io_apic_read(void *ioapic_base, u32 reg);
void io_apic_write(void *ioapic_base, u32 reg, u32 value); void io_apic_write(void *ioapic_base, u32 reg, u32 value);
void set_ioapic_id(void *ioapic_base, u8 ioapic_id); void set_ioapic_id(void *ioapic_base, u8 ioapic_id);
u8 get_ioapic_id(void *ioapic_base);
u8 get_ioapic_version(void *ioapic_base);
void setup_ioapic(void *ioapic_base, u8 ioapic_id); void setup_ioapic(void *ioapic_base, u8 ioapic_id);
void clear_ioapic(void *ioapic_base); void clear_ioapic(void *ioapic_base);

10
src/arch/x86/ioapic.c
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@ -109,6 +109,16 @@ void set_ioapic_id(void *ioapic_base, u8 ioapic_id)
} }
u8 get_ioapic_id(void *ioapic_base)
{
return (io_apic_read(ioapic_base, 0x00) >> 24) & 0x0f;
}
u8 get_ioapic_version(void *ioapic_base)
{
return io_apic_read(ioapic_base, 0x01) & 0xff;
}
void setup_ioapic_helper(void *ioapic_base, u8 ioapic_id, bool irq_on_fsb, void setup_ioapic_helper(void *ioapic_base, u8 ioapic_id, bool irq_on_fsb,
bool enable_virtual_wire) bool enable_virtual_wire)
{ {

5
src/soc/intel/xeon_sp/lpc.c
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@ -1,7 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */ /* SPDX-License-Identifier: GPL-2.0-or-later */
#include <console/console.h> #include <console/console.h>
#include <arch/ioapic.h>
#include <intelblocks/lpc_lib.h> #include <intelblocks/lpc_lib.h>
#include <soc/iomap.h> #include <soc/iomap.h>
#include <soc/pcr_ids.h> #include <soc/pcr_ids.h>
@ -23,9 +22,7 @@ void lpc_soc_init(struct device *dev)
printk(BIOS_SPEW, "pch: lpc_init\n"); printk(BIOS_SPEW, "pch: lpc_init\n");
/* FSP configures IOAPIC and PCHInterrupt Config */ /* FSP configures IOAPIC and PCHInterrupt Config */
printk(BIOS_SPEW, "IOAPICID 0x%x, 0x%x\n", /* Should read back the ID to fill ACPI IOAPIC accordingly. */
io_apic_read((void *)IO_APIC_ADDR, 0x00),
((io_apic_read((void *)IO_APIC_ADDR, 0x00) & 0x0f000000) >> 24));
} }
void pch_lpc_soc_fill_io_resources(struct device *dev) void pch_lpc_soc_fill_io_resources(struct device *dev)

14
src/southbridge/intel/i82371eb/isa.c
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@ -54,23 +54,15 @@ static void isa_init(struct device *dev)
if (CONFIG(IOAPIC)) { if (CONFIG(IOAPIC)) {
u16 reg16; u16 reg16;
u8 ioapic_id = 2; u8 ioapic_id = 2;
volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR);
volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10);
/* Enable IOAPIC. */ /* Enable IOAPIC. */
reg16 = pci_read_config16(dev, XBCS); reg16 = pci_read_config16(dev, XBCS);
reg16 |= (1 << 8); /* APIC Chip Select */ reg16 |= (1 << 8); /* APIC Chip Select */
pci_write_config16(dev, XBCS, reg16); pci_write_config16(dev, XBCS, reg16);
/* Set the IOAPIC ID. */ /* Set and verify the IOAPIC ID. */
*ioapic_index = 0; set_ioapic_id(VIO_APIC_VADDR, ioapic_id);
*ioapic_data = ioapic_id << 24; if (ioapic_id != get_ioapic_id(VIO_APIC_VADDR))
/* Read back and verify the IOAPIC ID. */
*ioapic_index = 0;
reg32 = (*ioapic_data >> 24) & 0x0f;
printk(BIOS_DEBUG, "IOAPIC ID = %x\n", reg32);
if (reg32 != ioapic_id)
die("IOAPIC error!\n"); die("IOAPIC error!\n");
} }
} }