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amd/olivehillplus: Fix PCIe lane number comments. 

Correct the GPP PCIe lane number comments so that they match the code.

Change-Id: If27c6a55ebedb0927dd9e8c7c9a833194e129a25
Signed-off-by: Derek Waldner <derek.waldner.os@gmail.com>
Reviewed-on: https://review.coreboot.org/15095
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Derek Waldner 2016-06-06 13:54:26 -05:00 committed by Martin Roth
parent d02685b053
commit 4025e26fc5
1 changed files with 5 additions and 4 deletions
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9
src/mainboard/amd/olivehillplus/OemCustomize.c
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@ -18,6 +18,7 @@
#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE #define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE
static const PCIe_PORT_DESCRIPTOR PortList [] = { static const PCIe_PORT_DESCRIPTOR PortList [] = {
/* Initialize Port descriptor (PCIe port, Lane 3, PCI Device 2, Function 5) */
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 3, 3), PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 3, 3),
@ -27,7 +28,7 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = {
PcieGenMaxSupported, PcieGenMaxSupported,
AspmDisabled, 0x01, 0) AspmDisabled, 0x01, 0)
}, },
/* Initialize Port descriptor (PCIe port, Lanes 1, PCI Device Number 2, ...) */ /* Initialize Port descriptor (PCIe port, Lane 2, PCI Device 2, Function 4) */
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 2, 2), PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 2, 2),
@ -37,7 +38,7 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = {
PcieGenMaxSupported, PcieGenMaxSupported,
AspmDisabled, 0x02, 0) AspmDisabled, 0x02, 0)
}, },
/* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2, ...) */ /* Initialize Port descriptor (PCIe port, Lane 1, PCI Device 2, Function 3) */
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 1, 1), PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 1, 1),
@ -47,7 +48,7 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = {
PcieGenMaxSupported, PcieGenMaxSupported,
AspmDisabled, 0x03, 0) AspmDisabled, 0x03, 0)
}, },
/* Initialize Port descriptor (PCIe port, Lanes 3, PCI Device Number 2, ...) */ /* Initialize Port descriptor (PCIe port, Lane 0, PCI Device 2, Function 2) */
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 0), PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 0),
@ -57,7 +58,7 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = {
PcieGenMaxSupported, PcieGenMaxSupported,
AspmDisabled, 0x04, 0) AspmDisabled, 0x04, 0)
}, },
/* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 4, ...) */ /* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device 2, Function 1) */
{ {
DESCRIPTOR_TERMINATE_LIST, DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 7), PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 7),