nb/intel/sandybridge/gma: Use common init_igd_opregion method
Use common init_igd_opregion method. Change-Id: Ia10a28d05b611a59f787b53f9736b3b76a19ea4a Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/19908 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Patrick Rudolph
Nico Huber
parent
5c82026ca6
commit
402e9c18dd
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@ -17,6 +17,7 @@
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config NORTHBRIDGE_INTEL_SANDYBRIDGE
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bool
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select NORTHBRIDGE_INTEL_COMMON_MRC_CACHE
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select NORTHBRIDGE_INTEL_COMMON_GMA_OPREGION
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select CPU_INTEL_MODEL_206AX
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select HAVE_DEBUG_RAM_SETUP
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select INTEL_GMA_ACPI
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@ -25,6 +26,7 @@ config NORTHBRIDGE_INTEL_SANDYBRIDGE
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config NORTHBRIDGE_INTEL_IVYBRIDGE
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bool
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select NORTHBRIDGE_INTEL_COMMON_MRC_CACHE
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select NORTHBRIDGE_INTEL_COMMON_GMA_OPREGION
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select CPU_INTEL_MODEL_306AX
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select HAVE_DEBUG_RAM_SETUP
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select INTEL_GMA_ACPI
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@ -16,18 +16,12 @@
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*/
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#include <types.h>
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#include <string.h>
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#include <console/console.h>
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#include <arch/io.h>
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#include <arch/acpi.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <drivers/intel/gma/i915.h>
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#include <arch/acpigen.h>
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#include "sandybridge.h"
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#include <cbmem.h>
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#include <drivers/intel/gma/intel_bios.h>
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#include <southbridge/intel/bd82x6x/pch.h>
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unsigned long acpi_fill_mcfg(unsigned long current)
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@ -75,140 +69,6 @@ unsigned long acpi_fill_mcfg(unsigned long current)
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return current;
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}
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static void *get_intel_vbios(void)
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{
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/* This should probably be looking at CBFS or we should always
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* deploy the VBIOS on Intel systems, even if we don't run it
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* in coreboot (e.g. SeaBIOS only scenarios).
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*/
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u8 *vbios = (u8 *)0xc0000;
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optionrom_header_t *oprom = (optionrom_header_t *)vbios;
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optionrom_pcir_t *pcir = (optionrom_pcir_t *)(vbios +
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oprom->pcir_offset);
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printk(BIOS_DEBUG, "GET_VBIOS: %x %x %x %x %x\n",
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oprom->signature, pcir->vendor, pcir->classcode[0],
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pcir->classcode[1], pcir->classcode[2]);
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if ((oprom->signature == OPROM_SIGNATURE) &&
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(pcir->vendor == PCI_VENDOR_ID_INTEL) &&
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(pcir->classcode[0] == 0x00) &&
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(pcir->classcode[1] == 0x00) &&
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(pcir->classcode[2] == 0x03))
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return (void *)vbios;
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return NULL;
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}
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static int init_opregion_vbt(igd_opregion_t *opregion)
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{
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void *vbios;
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vbios = get_intel_vbios();
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if (!vbios) {
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printk(BIOS_DEBUG, "VBIOS not found.\n");
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return 1;
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}
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printk(BIOS_DEBUG, " ... VBIOS found at %p\n", vbios);
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optionrom_header_t *oprom = (optionrom_header_t *)vbios;
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optionrom_vbt_t *vbt = (optionrom_vbt_t *)(vbios +
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oprom->vbt_offset);
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if (read32(vbt->hdr_signature) != VBT_SIGNATURE) {
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printk(BIOS_DEBUG, "VBT not found!\n");
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return 1;
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}
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memcpy(opregion->header.vbios_version, vbt->coreblock_biosbuild, 4);
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memcpy(opregion->vbt.gvd1, vbt, vbt->hdr_vbt_size < 7168 ?
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vbt->hdr_vbt_size : 7168);
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return 0;
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}
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/* Initialize IGD OpRegion, called from ACPI code */
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int init_igd_opregion(igd_opregion_t *opregion)
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{
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device_t igd;
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u16 reg16;
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memset((void *)opregion, 0, sizeof(igd_opregion_t));
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// FIXME if IGD is disabled, we should exit here.
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memcpy(&opregion->header.signature, IGD_OPREGION_SIGNATURE,
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sizeof(opregion->header.signature));
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/* 8kb */
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opregion->header.size = sizeof(igd_opregion_t) / 1024;
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opregion->header.version = IGD_OPREGION_VERSION;
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// FIXME We just assume we're mobile for now
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opregion->header.mailboxes = MAILBOXES_MOBILE;
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// TODO Initialize Mailbox 1
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// TODO Initialize Mailbox 3
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opregion->mailbox3.bclp = IGD_BACKLIGHT_BRIGHTNESS;
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opregion->mailbox3.pfit = IGD_FIELD_VALID | IGD_PFIT_STRETCH;
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opregion->mailbox3.pcft = 0; // should be (IMON << 1) & 0x3e
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opregion->mailbox3.cblv = IGD_FIELD_VALID | IGD_INITIAL_BRIGHTNESS;
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opregion->mailbox3.bclm[0] = IGD_WORD_FIELD_VALID + 0x0000;
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opregion->mailbox3.bclm[1] = IGD_WORD_FIELD_VALID + 0x0a19;
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opregion->mailbox3.bclm[2] = IGD_WORD_FIELD_VALID + 0x1433;
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opregion->mailbox3.bclm[3] = IGD_WORD_FIELD_VALID + 0x1e4c;
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opregion->mailbox3.bclm[4] = IGD_WORD_FIELD_VALID + 0x2866;
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opregion->mailbox3.bclm[5] = IGD_WORD_FIELD_VALID + 0x327f;
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opregion->mailbox3.bclm[6] = IGD_WORD_FIELD_VALID + 0x3c99;
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opregion->mailbox3.bclm[7] = IGD_WORD_FIELD_VALID + 0x46b2;
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opregion->mailbox3.bclm[8] = IGD_WORD_FIELD_VALID + 0x50cc;
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opregion->mailbox3.bclm[9] = IGD_WORD_FIELD_VALID + 0x5ae5;
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opregion->mailbox3.bclm[10] = IGD_WORD_FIELD_VALID + 0x64ff;
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init_opregion_vbt(opregion);
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/* TODO This needs to happen in S3 resume, too.
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* Maybe it should move to the finalize handler
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*/
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igd = dev_find_slot(0, PCI_DEVFN(0x2, 0));
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pci_write_config32(igd, ASLS, (u32)opregion);
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reg16 = pci_read_config16(igd, SWSCI);
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reg16 &= ~(1 << 0);
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reg16 |= (1 << 15);
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pci_write_config16(igd, SWSCI, reg16);
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/* clear dmisci status */
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reg16 = inw(DEFAULT_PMBASE + TCO1_STS);
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reg16 |= DMISCI_STS; // reference code does an &=
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outw(DEFAULT_PMBASE + TCO1_STS, reg16);
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/* clear acpi tco status */
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outl(DEFAULT_PMBASE + GPE0_STS, TCOSCI_STS);
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/* enable acpi tco scis */
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reg16 = inw(DEFAULT_PMBASE + GPE0_EN);
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reg16 |= TCOSCI_EN;
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outw(DEFAULT_PMBASE + GPE0_EN, reg16);
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return 0;
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}
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void *igd_make_opregion(void)
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{
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igd_opregion_t *opregion;
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printk(BIOS_DEBUG, "ACPI: * IGD OpRegion\n");
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opregion = cbmem_add(CBMEM_ID_IGD_OPREGION, sizeof(*opregion));
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if (opregion)
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init_igd_opregion(opregion);
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return opregion;
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}
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static unsigned long acpi_fill_dmar(unsigned long current)
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{
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const struct device *const igfx = dev_find_slot(0, PCI_DEVFN(2, 0));
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@ -25,6 +25,7 @@
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#include <cpu/x86/msr.h>
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#include <cpu/x86/mtrr.h>
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#include <southbridge/intel/bd82x6x/nvs.h>
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#include <northbridge/intel/common/gma_opregion.h>
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#include <cbmem.h>
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#include "chip.h"
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@ -652,17 +653,38 @@ static void gma_ssdt(device_t device)
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drivers_intel_gma_displays_ssdt_generate(gfx);
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}
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/* Enable SCI to ACPI _GPE._L06 */
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static void gma_enable_swsci(void)
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{
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u16 reg16;
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/* clear DMISCI status */
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reg16 = inw(DEFAULT_PMBASE + TCO1_STS);
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reg16 &= DMISCI_STS;
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outw(DEFAULT_PMBASE + TCO1_STS, reg16);
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/* clear acpi tco status */
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outl(DEFAULT_PMBASE + GPE0_STS, TCOSCI_STS);
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/* enable acpi tco scis */
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reg16 = inw(DEFAULT_PMBASE + GPE0_EN);
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reg16 |= TCOSCI_EN;
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outw(DEFAULT_PMBASE + GPE0_EN, reg16);
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}
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static unsigned long
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gma_write_acpi_tables(struct device *const dev,
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unsigned long current,
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struct acpi_rsdp *const rsdp)
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{
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igd_opregion_t *opregion;
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igd_opregion_t *opregion = (igd_opregion_t *)current;
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global_nvs_t *gnvs;
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// FIXME: Replace by common VBT implementation writing to current
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opregion = igd_make_opregion();
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if (opregion) {
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if (init_igd_opregion(opregion) != CB_SUCCESS)
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return current;
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current += sizeof(igd_opregion_t);
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/* GNVS has been already set up */
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gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
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if (gnvs) {
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@ -671,8 +693,10 @@ gma_write_acpi_tables(struct device *const dev,
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} else {
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printk(BIOS_ERR, "Error: GNVS table not found.\n");
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}
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}
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gma_enable_swsci();
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current = acpi_align_current(current);
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return current;
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}
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@ -237,11 +237,6 @@ struct acpi_rsdp;
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unsigned long northbridge_write_acpi_tables(device_t device, unsigned long start, struct acpi_rsdp *rsdp);
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#endif
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#if !defined(__PRE_RAM__)
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#include <drivers/intel/gma/opregion.h>
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int init_igd_opregion(igd_opregion_t *igd_opregion);
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#endif
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#endif
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#endif
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#endif /* __NORTHBRIDGE_INTEL_SANDYBRIDGE_SANDYBRIDGE_H__ */
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