mb/up/squared: Add mainboard
Works:
- bootblock, romstage, ramstage
- Serial console UART0, UART1
- SPI flash console
- iGPU init with libgfxinit
- LAN1, LAN2
- USB2, USB3
- HDMI, DisplayPort
- eMMC
- flashing with flashrom externally
WIP:
- Documentation
- VGA
For some reason Seabios can not find the CBFS region
and therefore it can't load seavgabios, but generally
it is working as soon as Linux is booted.
- ACPI
Works not:
- Devices needs proper configuration
- Seabios can't find CBFS region
Untested:
- GPIO pin header
- 60 pin EXHAT
- Camera interface
- MIPI-CSI2 2-lane (2MP)
- MIPI-CSI2 4-lane (8MP)
- SATA3
- USB3 OTG
- embedded DisplayPort
- M.2 slot
- mini PCIe
- flashing with flashrom internally using Linux
Change-Id: Ia913534ec176fc600fcd4ce3af335ebe682b0ed4
Signed-off-by: Felix Singer <felix.singer@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31378
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
This commit is contained in:
Felix Singer
Patrick Rudolph
parent
fa40e82270
commit
402fe20e3e
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@ -82,3 +82,7 @@ The boards in this section are not real mainboards, but emulators.
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## Supermicro
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- [X10SLM+-F](supermicro/x10slm-f.md)
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## UP
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- [Squared](up/squared/index.md)
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Binary file not shown.
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After Width: | Height: | Size: 38 KiB |
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@ -0,0 +1,99 @@
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# Squared
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## Overview
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### Top
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![][overview_top]
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### Bottom
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![][overview_bottom]
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## Mainboard components
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### Platform
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```eval_rst
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+------------------+----------------------------------+
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| CPU | Intel Atom, Celeron, Pentium |
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+------------------+----------------------------------+
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| PCH | Intel Apollo Lake |
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+------------------+----------------------------------+
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| EC / Super IO | N/A |
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+------------------+----------------------------------+
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| Coprocessor | Intel TXE 3.0 |
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+------------------+----------------------------------+
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```
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### Flash chip
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```eval_rst
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+---------------------+------------+
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| Type | Value |
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+=====================+============+
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| Socketed flash | no |
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+---------------------+------------+
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| Vendor | Winbond |
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+---------------------+------------+
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| Model | W25Q128FW |
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+---------------------+------------+
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| Voltage | 1.8V |
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+---------------------+------------+
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| Size | 16 MiB |
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+---------------------+------------+
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| Package | SOIC-8 |
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+---------------------+------------+
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| Write protection | No |
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+---------------------+------------+
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| Internal flashing | No |
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+---------------------+------------+
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| In curcuit flashing | Yes |
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+---------------------+------------+
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```
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## Board status
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### Working
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- bootblock, romstage, ramstage
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- Serial console UART0, UART1
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- SPI flash console
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- iGPU init with libgfxinit
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- LAN1, LAN2
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- USB2, USB3
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- HDMI, DisplayPort
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- eMMC
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- flashing with flashrom externally
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### Work in progress
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- Documentation
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- ACPI
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### Not working / Known issues
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- Generally SeaBIOS works, but it can't find the CBFS region and therefore it can't load seavgabios. This is because of changes at the Apollolake platform.
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### Untested
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- GPIO pin header
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- 60 pin EXHAT
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- Camera interface
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- MIPI-CSI2 2-lane (2MP)
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- MIPI-CSI2 4-lane (8MP)
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- SATA3
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- USB3 OTG
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- embedded DisplayPort
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- M.2 slot
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- mini PCIe
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- flashing with flashrom internally using Linux
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## Building and flashing coreboot
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### Building
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```bash
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make distclean
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touch .config
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./util/scripts/config --enable VENDOR_UP
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./util/scripts/config --enable BOARD_UP_SQUARED
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./util/scripts/config --enable NEED_IFWI
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./util/scripts/config --enable HAVE_IFD_BIN
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./util/scripts/config --set-str IFWI_FILE_NAME "<path_to_your_bios_region>"
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./util/scripts/config --set-str IFD_BIN_PATH "<path_to_your_ifd_region>"
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make olddefconfig
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```
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### Flashing
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[overview_top]: top.jpg
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[overview_bottom]: bottom.jpg
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Binary file not shown.
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After Width: | Height: | Size: 33 KiB |
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@ -0,0 +1,16 @@
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if VENDOR_UP
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choice
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prompt "Mainboard model"
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source "src/mainboard/up/*/Kconfig.name"
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endchoice
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source "src/mainboard/up/*/Kconfig"
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config MAINBOARD_VENDOR
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string
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default "UP"
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endif
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@ -0,0 +1,2 @@
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config VENDOR_UP
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bool "UP"
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@ -0,0 +1,88 @@
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if BOARD_UP_SQUARED
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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select USE_BLOBS
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select ADD_FSP_BINARIES
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select FSP_USE_REPO
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select HAVE_ACPI_TABLES
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select HAVE_ACPI_RESUME
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select INTEL_GMA_HAVE_VBT
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select INTEL_LPSS_UART_FOR_CONSOLE
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select SOC_INTEL_APOLLOLAKE
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select BOARD_ROMSIZE_KB_16384
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select ONBOARD_VGA_IS_PRIMARY
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select MAINBOARD_HAS_LIBGFXINIT
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config VBOOT
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select VBOOT_NO_BOARD_SUPPORT
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select GBB_FLAG_DISABLE_LID_SHUTDOWN
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select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC
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select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC
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select GBB_FLAG_DISABLE_FWMP
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config GBB_HWID
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string
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depends on VBOOT
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default "UPSQUARED"
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config MAINBOARD_DIR
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string
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default "up/squared"
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config MAINBOARD_VENDOR
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string
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default "Up"
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config MAINBOARD_PART_NUMBER
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string
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default "Squared"
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config FMDFILE
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string
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default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/upsquared.fmd" if !VBOOT
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default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot-ro.fmd" if !VBOOT_SLOTS_RW_A
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default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot-roa.fmd" if VBOOT_SLOTS_RW_A && !VBOOT_SLOTS_RW_AB
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default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot-roab.fmd" if VBOOT_SLOTS_RW_AB
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config SUBSYSTEM_VENDOR_ID
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hex
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default 0x8086
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config SUBSYSTEM_DEVICE_ID
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hex
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default 0x7270
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config VGA_BIOS_ID
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string
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default "8086,5a85"
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config PXE_ROM_ID
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string
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default "10ec,8168"
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config MAX_CPUS
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int
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default 2
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config UART_FOR_CONSOLE
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int
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default 0
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config IFWI_FMAP_NAME
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string
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default "IFWI"
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config POST_IO
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bool
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default n
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config POST_DEVICE
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bool
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default n
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config CONSOLE_POST
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bool
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default y
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endif
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@ -0,0 +1,2 @@
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config BOARD_UP_SQUARED
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bool "Squared"
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@ -0,0 +1,7 @@
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bootblock-y += bootblock.c
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romstage-y += romstage.c
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ramstage-y += ramstage.c
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ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
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@ -0,0 +1,7 @@
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Vendor name: Up
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Board name: Squared
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Category: mini
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ROM protocol: SPI
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ROM socketed: n
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Flashrom support: n
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Release year: 2017
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@ -0,0 +1,22 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2016 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <bootblock_common.h>
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#include <intelblocks/lpc_lib.h>
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void bootblock_mainboard_init(void)
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{
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lpc_configure_pads();
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}
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Binary file not shown.
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@ -0,0 +1,50 @@
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chip soc/intel/apollolake
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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device domain 0 on
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device pci 00.0 on end # - Host Bridge
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device pci 00.1 off end # - DPTF
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device pci 00.2 off end # - NPK
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device pci 02.0 on end # - Gen
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device pci 03.0 off end # - Iunit
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device pci 0d.0 off end # - P2SB
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device pci 0d.1 off end # - PMC
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device pci 0d.2 off end # - SPI
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device pci 0d.3 off end # - Shared SRAM
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device pci 0e.0 on end # - Audio
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device pci 0f.0 on end # - TXE
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device pci 11.0 off end # - ISH
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device pci 12.0 on end # - SATA
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device pci 13.0 on end # - PCIe-A 1 - PcieRootPort[2]
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device pci 13.1 on end # - PCIe-A 2 - PcieRootPort[3]
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device pci 13.2 on end # - PCIe-A 3 - PcieRootPort[4]
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device pci 13.3 on end # - PCIe-A 4 - PcieRootPort[5]
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device pci 14.0 on end # - PCIe-B 1 - PcieRootPort[0]
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device pci 14.1 on end # - PCIe-B 2 - PcieRootPort[1]
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device pci 15.0 on end # - XHCI
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device pci 15.1 on end # - XDCI
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device pci 16.0 on end # - I2C 0
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device pci 16.1 on end # - I2C 1
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device pci 16.2 on end # - I2C 2
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device pci 16.3 on end # - I2C 3
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device pci 17.0 on end # - I2C 4
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device pci 17.1 on end # - I2C 5
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device pci 17.2 on end # - I2C 6
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device pci 17.3 on end # - I2C 7
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device pci 18.0 on end # - HSUART 0
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device pci 18.1 on end # - HSUART 1
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device pci 18.2 off end # - UART 2
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device pci 18.3 off end # - UART 3
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device pci 19.0 on end # - SPI 0
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device pci 19.1 on end # - SPI 1
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device pci 19.2 on end # - SPI 2
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device pci 1a.0 on end # - PWM
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device pci 1b.0 off end # - SDCARD
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device pci 1c.0 on end # - eMMC
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device pci 1e.0 on end # - SDIO
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device pci 1f.0 on end # - LPC
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device pci 1f.1 on end # - SMBUS
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end
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end
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@ -0,0 +1,43 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2016 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/acpi.h>
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DefinitionBlock(
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"dsdt.aml",
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"DSDT",
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0x02, // DSDT revision: ACPI v2.0 and up
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OEM_ID,
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ACPI_TABLE_CREATOR,
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0x20110725 // OEM revision
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)
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{
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/* global NVS and variables */
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#include <soc/intel/apollolake/acpi/globalnvs.asl>
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/* CPU */
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#include <cpu/intel/common/acpi/cpu.asl>
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Scope (\_SB) {
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Device (PCI0)
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{
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#include <soc/intel/apollolake/acpi/northbridge.asl>
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#include <soc/intel/apollolake/acpi/southbridge.asl>
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#include <soc/intel/apollolake/acpi/pch_hda.asl>
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}
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}
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/* Chipset specific sleep states */
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#include <soc/intel/apollolake/acpi/sleepstates.asl>
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}
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@ -0,0 +1,32 @@
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--
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-- This file is part of the coreboot project.
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--
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||||
-- This program is free software; you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation; either version 2 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
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with HW.GFX.GMA;
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with HW.GFX.GMA.Display_Probing;
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use HW.GFX.GMA;
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use HW.GFX.GMA.Display_Probing;
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private package GMA.Mainboard is
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ports : constant Port_List :=
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(DP1,
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DP2,
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DP3,
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HDMI1,
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HDMI2,
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HDMI3,
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others => Disabled);
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end GMA.Mainboard;
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|
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@ -0,0 +1,773 @@
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/*
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* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2019 Felix Singer <felix.singer@9elements.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
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#include <soc/gpio.h>
|
||||
|
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#ifndef GPIO_H
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#define GPIO_H
|
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|
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static const struct pad_config gpio_table[] = {
|
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// ********************************
|
||||
// ******* GPIO Group North *******
|
||||
// ********************************
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||||
// *GPIO
|
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_PAD_CFG_STRUCT(GPIO_0, 0x04000102, 0x00000000),
|
||||
|
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// *GPIO
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_PAD_CFG_STRUCT(GPIO_1, 0x04000102, 0x00000000),
|
||||
|
||||
// *GPIO
|
||||
_PAD_CFG_STRUCT(GPIO_2, 0x04000100, 0x00000000),
|
||||
|
||||
// *GPIO
|
||||
_PAD_CFG_STRUCT(GPIO_3, 0x04000100, 0x00000000),
|
||||
|
||||
// *GPIO
|
||||
_PAD_CFG_STRUCT(GPIO_4, 0x04000100, 0x00000000),
|
||||
|
||||
// *GPIO
|
||||
_PAD_CFG_STRUCT(GPIO_5, 0x44000100, 0x00000000),
|
||||
|
||||
// *GPIO
|
||||
_PAD_CFG_STRUCT(GPIO_6, 0x44000201, 0x00000000),
|
||||
|
||||
// *GPIO
|
||||
_PAD_CFG_STRUCT(GPIO_7, 0x44000201, 0x00000000),
|
||||
|
||||
// *GPIO
|
||||
_PAD_CFG_STRUCT(GPIO_8, 0x44000201, 0x00000000),
|
||||
|
||||
// *GPIO
|
||||
_PAD_CFG_STRUCT(GPIO_9, 0x44000201, 0x00000000),
|
||||
|
||||
// *GPIO
|
||||
_PAD_CFG_STRUCT(GPIO_10, 0x44000201, 0x00000000),
|
||||
|
||||
// *GPIO
|
||||
_PAD_CFG_STRUCT(GPIO_11, 0x44000201, 0x00000000),
|
||||
|
||||
// *GPIO
|
||||
_PAD_CFG_STRUCT(GPIO_12, 0x44000201, 0x00000000),
|
||||
|
||||
// *GPIO
|
||||
_PAD_CFG_STRUCT(GPIO_13, 0x44000100, 0x00000000),
|
||||
|
||||
// *GPIO
|
||||
_PAD_CFG_STRUCT(GPIO_14, 0x44000102, 0x00000000),
|
||||
|
||||
// *GPIO
|
||||
_PAD_CFG_STRUCT(GPIO_15, 0x44000102, 0x00000000),
|
||||
|
||||
// *GPIO
|
||||
_PAD_CFG_STRUCT(GPIO_16, 0x40880102, 0x00024000),
|
||||
|
||||
// *GPIO
|
||||
_PAD_CFG_STRUCT(GPIO_17, 0x44000201, 0x00000000),
|
||||
|
||||
// *GPIO
|
||||
_PAD_CFG_STRUCT(GPIO_18, 0x44000201, 0x00000000),
|
||||
|
||||
// *GPIO
|
||||
_PAD_CFG_STRUCT(GPIO_19, 0x44000201, 0x00003000),
|
||||
|
||||
// *GPIO
|
||||
_PAD_CFG_STRUCT(GPIO_20, 0x44000100, 0x00000000),
|
||||
|
||||
// *GPIO
|
||||
_PAD_CFG_STRUCT(GPIO_21, 0x44000201, 0x00000000),
|
||||
|
||||
// *GPIO
|
||||
_PAD_CFG_STRUCT(GPIO_22, 0x44000102, 0x00000000),
|
||||
|
||||
// *GPIO
|
||||
_PAD_CFG_STRUCT(GPIO_23, 0x44000100, 0x00000000),
|
||||
|
||||
// *GPIO
|
||||
_PAD_CFG_STRUCT(GPIO_24, 0x44000102, 0x00000000),
|
||||
|
||||
// *GPIO
|
||||
_PAD_CFG_STRUCT(GPIO_25, 0x44000102, 0x00000000),
|
||||
|
||||
// *GPIO
|
||||
_PAD_CFG_STRUCT(GPIO_26, 0x44000100, 0x00000000),
|
||||
|
||||
// *GPIO
|
||||
_PAD_CFG_STRUCT(GPIO_27, 0x44000201, 0x00000000),
|
||||
|
||||
// *GPIO
|
||||
_PAD_CFG_STRUCT(GPIO_28, 0x44000102, 0x00003000),
|
||||
|
||||
// *GPIO
|
||||
_PAD_CFG_STRUCT(GPIO_29, 0x44000102, 0x00003000),
|
||||
|
||||
// *GPIO
|
||||
_PAD_CFG_STRUCT(GPIO_30, 0x44000102, 0x00003000),
|
||||
|
||||
// *GPIO
|
||||
_PAD_CFG_STRUCT(GPIO_31, 0x44000102, 0x00003000),
|
||||
|
||||
// *GPIO
|
||||
_PAD_CFG_STRUCT(GPIO_32, 0x44000102, 0x00000000),
|
||||
|
||||
// *GPIO
|
||||
_PAD_CFG_STRUCT(GPIO_33, 0x44000102, 0x00000000),
|
||||
|
||||
// PWM0
|
||||
_PAD_CFG_STRUCT(GPIO_34, 0x44000400, 0x00001000),
|
||||
|
||||
// PWM1
|
||||
_PAD_CFG_STRUCT(GPIO_35, 0x44000400, 0x00001000),
|
||||
|
||||
// *GPIO
|
||||
_PAD_CFG_STRUCT(GPIO_36, 0x44000201, 0x00000000),
|
||||
|
||||
// PWM3
|
||||
_PAD_CFG_STRUCT(GPIO_37, 0x04000400, 0x00001000),
|
||||
|
||||
// LPSS_UART0_RXD
|
||||
_PAD_CFG_STRUCT(GPIO_38, 0x44000402, 0x00023100),
|
||||
|
||||
// LPSS_UART0_TXD
|
||||
_PAD_CFG_STRUCT(GPIO_39, 0x44000400, 0x00003100),
|
||||
|
||||
// LPSS_UART0_RTS_N
|
||||
_PAD_CFG_STRUCT(GPIO_40, 0x44000400, 0x00003100),
|
||||
|
||||
// LPSS_UART0_CTS_N
|
||||
_PAD_CFG_STRUCT(GPIO_41, 0x44000402, 0x00023100),
|
||||
|
||||
// LPSS_UART1_RXD
|
||||
_PAD_CFG_STRUCT(GPIO_42, 0x44000402, 0x00023100),
|
||||
|
||||
// LPSS_UART1_TXD
|
||||
_PAD_CFG_STRUCT(GPIO_43, 0x44000400, 0x0001f100),
|
||||
|
||||
// LPSS_UART1_RTS_N
|
||||
_PAD_CFG_STRUCT(GPIO_44, 0x44000400, 0x00003100),
|
||||
|
||||
// LPSS_UART1_CTS_N
|
||||
_PAD_CFG_STRUCT(GPIO_45, 0x44000402, 0x0001c100),
|
||||
|
||||
// *GPIO
|
||||
_PAD_CFG_STRUCT(GPIO_46, 0x44000100, 0x00000000),
|
||||
|
||||
// *GPIO
|
||||
_PAD_CFG_STRUCT(GPIO_47, 0x44000100, 0x00000000),
|
||||
|
||||
// *GPIO
|
||||
_PAD_CFG_STRUCT(GPIO_48, 0x44000100, 0x00000000),
|
||||
|
||||
// *GPIO
|
||||
_PAD_CFG_STRUCT(GPIO_49, 0x44000100, 0x00000000),
|
||||
|
||||
// *GPIO
|
||||
_PAD_CFG_STRUCT(GPIO_62, 0x44000100, 0x00000000),
|
||||
|
||||
// *GPIO
|
||||
_PAD_CFG_STRUCT(GPIO_63, 0x44000100, 0x00000000),
|
||||
|
||||
// *GPIO
|
||||
_PAD_CFG_STRUCT(GPIO_64, 0x44000100, 0x00000000),
|
||||
|
||||
// *GPIO
|
||||
_PAD_CFG_STRUCT(GPIO_65, 0x44000100, 0x00000000),
|
||||
|
||||
// *GPIO
|
||||
_PAD_CFG_STRUCT(GPIO_66, 0x44000100, 0x00000000),
|
||||
|
||||
// *GPIO
|
||||
_PAD_CFG_STRUCT(GPIO_67, 0x44000100, 0x00000000),
|
||||
|
||||
// *GPIO
|
||||
_PAD_CFG_STRUCT(GPIO_68, 0x44000100, 0x00000000),
|
||||
|
||||
// *GPIO
|
||||
_PAD_CFG_STRUCT(GPIO_69, 0x44000100, 0x00000000),
|
||||
|
||||
// *GPIO
|
||||
_PAD_CFG_STRUCT(GPIO_70, 0x44000100, 0x00000000),
|
||||
|
||||
// *GPIO
|
||||
_PAD_CFG_STRUCT(GPIO_71, 0x44000100, 0x00000000),
|
||||
|
||||
// *GPIO
|
||||
_PAD_CFG_STRUCT(GPIO_72, 0x44000200, 0x00001000),
|
||||
|
||||
// *GPIO
|
||||
_PAD_CFG_STRUCT(GPIO_73, 0x44000200, 0x00001000),
|
||||
|
||||
// *JTAG_TCK
|
||||
_PAD_CFG_STRUCT(TCK, 0x44000400, 0x00c3d000),
|
||||
|
||||
// *JTAG_TRST_N
|
||||
_PAD_CFG_STRUCT(TRST_B, 0x44000400, 0x00c3d000),
|
||||
|
||||
// *JTAG_TMS
|
||||
_PAD_CFG_STRUCT(TMS, 0x44000400, 0x00c3f000),
|
||||
|
||||
// *JTAG_TDI
|
||||
_PAD_CFG_STRUCT(TDI, 0x44000400, 0x00c3f000),
|
||||
|
||||
// *JTAG_PMODE
|
||||
_PAD_CFG_STRUCT(CX_PMODE, 0x44000400, 0x00c3c000),
|
||||
|
||||
// *JTAG_PREQ_N
|
||||
_PAD_CFG_STRUCT(CX_PREQ_B, 0x44000402, 0x00c3f000),
|
||||
|
||||
// *JTAGX
|
||||
_PAD_CFG_STRUCT(JTAGX, 0x44000402, 0x00c3f000),
|
||||
|
||||
// *JTAG_PRDY_N
|
||||
_PAD_CFG_STRUCT(CX_PRDY_B, 0x44000402, 0x0043f000),
|
||||
|
||||
// *JTAG_TDO
|
||||
_PAD_CFG_STRUCT(TDO, 0x44000400, 0x0043f000),
|
||||
|
||||
// GPIO
|
||||
_PAD_CFG_STRUCT(CNV_BRI_DT, 0x44000201, 0x0003d000),
|
||||
|
||||
// GPIO
|
||||
_PAD_CFG_STRUCT(CNV_BRI_RSP, 0x44000201, 0x00002400),
|
||||
|
||||
// GPIO
|
||||
_PAD_CFG_STRUCT(CNV_RGI_DT, 0x44000201, 0x00000000),
|
||||
|
||||
// RESERVED
|
||||
// _PAD_CFG_STRUCT(CNV_RGI_RSP, 0xffffffff, 0xffffffff),
|
||||
|
||||
// GPIO
|
||||
_PAD_CFG_STRUCT(SVID0_ALERT_B, 0x44000100, 0x00000000),
|
||||
|
||||
// GPIO
|
||||
_PAD_CFG_STRUCT(SVID0_DATA, 0x44000100, 0x00000000),
|
||||
|
||||
// GPIO
|
||||
_PAD_CFG_STRUCT(SVID0_CLK, 0x44000100, 0x00000000),
|
||||
|
||||
|
||||
// ************************************
|
||||
// ******* GPIO Group NorthWest *******
|
||||
// ************************************
|
||||
// *DDI0_DDC_SDA
|
||||
_PAD_CFG_STRUCT(GPIO_187, 0x44000400, 0x0001f000),
|
||||
|
||||
// *DDI0_DDC_SCL
|
||||
_PAD_CFG_STRUCT(GPIO_188, 0x44000400, 0x0001f000),
|
||||
|
||||
// *DDI1_DDC_SDA
|
||||
_PAD_CFG_STRUCT(GPIO_189, 0x44000400, 0x00002c00),
|
||||
|
||||
// *DDI1_DDC_SCL
|
||||
_PAD_CFG_STRUCT(GPIO_190, 0x44000400, 0x00002c00),
|
||||
|
||||
// GPIO
|
||||
_PAD_CFG_STRUCT(GPIO_191, 0x44000100, 0x00000000),
|
||||
|
||||
// GPIO
|
||||
_PAD_CFG_STRUCT(GPIO_192, 0x44000100, 0x00000000),
|
||||
|
||||
// *PNL0_VDDEN
|
||||
_PAD_CFG_STRUCT(GPIO_193, 0x44000400, 0x00005000),
|
||||
|
||||
// *PNL0_BKLTEN
|
||||
_PAD_CFG_STRUCT(GPIO_194, 0x44000400, 0x00005000),
|
||||
|
||||
// *PNL0_BKLTCTL
|
||||
_PAD_CFG_STRUCT(GPIO_195, 0x44000400, 0x00005000),
|
||||
|
||||
// GPIO
|
||||
_PAD_CFG_STRUCT(GPIO_196, 0x44000100, 0x00000000),
|
||||
|
||||
// GPIO
|
||||
_PAD_CFG_STRUCT(GPIO_197, 0x44000100, 0x00000000),
|
||||
|
||||
// GPIO
|
||||
_PAD_CFG_STRUCT(GPIO_198, 0x44000100, 0x00000000),
|
||||
|
||||
// DDI1_HPD
|
||||
_PAD_CFG_STRUCT(GPIO_199, 0x44000800, 0x00003000),
|
||||
|
||||
// DDI0_HPD
|
||||
_PAD_CFG_STRUCT(GPIO_200, 0x44000802, 0x00003000),
|
||||
|
||||
// GPIO
|
||||
_PAD_CFG_STRUCT(GPIO_201, 0x44000100, 0x00000000),
|
||||
|
||||
// GPIO
|
||||
_PAD_CFG_STRUCT(GPIO_202, 0x44000100, 0x00000000),
|
||||
|
||||
// GPIO
|
||||
_PAD_CFG_STRUCT(GPIO_203, 0x44000102, 0x00000000),
|
||||
|
||||
// GPIO
|
||||
_PAD_CFG_STRUCT(GPIO_204, 0x44000102, 0x00000000),
|
||||
|
||||
// GPIO
|
||||
_PAD_CFG_STRUCT(PMC_SPI_FS0, 0x44000102, 0x00000000),
|
||||
|
||||
// DDI2_HPD
|
||||
_PAD_CFG_STRUCT(PMC_SPI_FS1, 0x44000802, 0x00003000),
|
||||
|
||||
// GPIO
|
||||
_PAD_CFG_STRUCT(PMC_SPI_FS2, 0x44000102, 0x00000000),
|
||||
|
||||
// GPIO
|
||||
_PAD_CFG_STRUCT(PMC_SPI_RXD, 0x44000100, 0x00000000),
|
||||
|
||||
// GPIO
|
||||
_PAD_CFG_STRUCT(PMC_SPI_TXD, 0x44000100, 0x00000000),
|
||||
|
||||
// GPIO
|
||||
_PAD_CFG_STRUCT(PMC_SPI_CLK, 0x44000100, 0x00000000),
|
||||
|
||||
// GPIO
|
||||
_PAD_CFG_STRUCT(PMIC_PWRGOOD, 0x44000203, 0x00002400),
|
||||
|
||||
// GPIO
|
||||
_PAD_CFG_STRUCT(PMIC_RESET_B, 0x44000102, 0x0003c000),
|
||||
|
||||
// GPIO
|
||||
_PAD_CFG_STRUCT(GPIO_213, 0x44000201, 0x00003000),
|
||||
|
||||
// GPIO
|
||||
_PAD_CFG_STRUCT(GPIO_214, 0x44000102, 0x00000000),
|
||||
|
||||
// GPIO
|
||||
_PAD_CFG_STRUCT(GPIO_215, 0x44000100, 0x00000000),
|
||||
|
||||
// *THERMTRIP_N
|
||||
_PAD_CFG_STRUCT(PMIC_THERMTRIP_B, 0x44000400, 0x00003000),
|
||||
|
||||
// GPIO
|
||||
_PAD_CFG_STRUCT(PMIC_STDBY, 0x44000201, 0x00001000),
|
||||
|
||||
// *PROCHOT_N
|
||||
_PAD_CFG_STRUCT(PROCHOT_B, 0x44000402, 0x00023000),
|
||||
|
||||
// RESERVED
|
||||
// _PAD_CFG_STRUCT(PMIC_I2C_SCL, 0xffffffff, 0xffffffff),
|
||||
|
||||
// RESERVED
|
||||
// _PAD_CFG_STRUCT(PMIC_I2C_SDA, 0xffffffff, 0xffffffff),
|
||||
|
||||
// *GPIO
|
||||
_PAD_CFG_STRUCT(GPIO_74, 0x44000100, 0x00000000),
|
||||
|
||||
// *GPIO
|
||||
_PAD_CFG_STRUCT(GPIO_75, 0x44000100, 0x00000000),
|
||||
|
||||
// *GPIO
|
||||
_PAD_CFG_STRUCT(GPIO_76, 0x44000100, 0x00000000),
|
||||
|
||||
// *GPIO
|
||||
_PAD_CFG_STRUCT(GPIO_77, 0x44000100, 0x00000000),
|
||||
|
||||
// *GPIO
|
||||
_PAD_CFG_STRUCT(GPIO_78, 0x44000100, 0x00000000),
|
||||
|
||||
// AVS_DMIC_CLK_A1
|
||||
_PAD_CFG_STRUCT(GPIO_79, 0x44000400, 0x0003d000),
|
||||
|
||||
// AVS_DMIC_CLK_B1
|
||||
_PAD_CFG_STRUCT(GPIO_80, 0x44000400, 0x0003d000),
|
||||
|
||||
// AVS_DMIC_DATA_1
|
||||
_PAD_CFG_STRUCT(GPIO_81, 0x44000400, 0x00025200),
|
||||
|
||||
// AVS_DMIC_CLK_AB2
|
||||
_PAD_CFG_STRUCT(GPIO_82, 0x44000400, 0x0003d000),
|
||||
|
||||
// AVS_DMIC_DATA_2
|
||||
_PAD_CFG_STRUCT(GPIO_83, 0x44000400, 0x00025200),
|
||||
|
||||
// AVS_I2S2_MCLK
|
||||
_PAD_CFG_STRUCT(GPIO_84, 0x44000400, 0x00001000),
|
||||
|
||||
// AVS_I2S2_BCLK
|
||||
_PAD_CFG_STRUCT(GPIO_85, 0x44000400, 0x0001d200),
|
||||
|
||||
// AVS_I2S2_WS_SYNC
|
||||
_PAD_CFG_STRUCT(GPIO_86, 0x44000402, 0x0001d200),
|
||||
|
||||
// AVS_I2S2_SDI
|
||||
_PAD_CFG_STRUCT(GPIO_87, 0x44000402, 0x0001f200),
|
||||
|
||||
// AVS_I2S2_SDO
|
||||
_PAD_CFG_STRUCT(GPIO_88, 0x44000400, 0x0001c200),
|
||||
|
||||
// *GPIO
|
||||
_PAD_CFG_STRUCT(GPIO_89, 0x44000100, 0x00000000),
|
||||
|
||||
// *GPIO
|
||||
_PAD_CFG_STRUCT(GPIO_90, 0x44000100, 0x00000000),
|
||||
|
||||
// *GPIO
|
||||
_PAD_CFG_STRUCT(GPIO_91, 0x44000100, 0x00000000),
|
||||
|
||||
// *GPIO
|
||||
_PAD_CFG_STRUCT(GPIO_92, 0x44000100, 0x00000000),
|
||||
|
||||
// *FST_SPI_CS0_N
|
||||
_PAD_CFG_STRUCT(GPIO_97, 0x44000402, 0x0003fc00),
|
||||
|
||||
// GPIO
|
||||
_PAD_CFG_STRUCT(GPIO_98, 0x44000100, 0x00000000),
|
||||
|
||||
// *FST_SPI_MOSI_IO0
|
||||
_PAD_CFG_STRUCT(GPIO_99, 0x44000400, 0x0003fc00),
|
||||
|
||||
// *FST_SPI_MISO_IO1
|
||||
_PAD_CFG_STRUCT(GPIO_100, 0x44000402, 0x0003fc00),
|
||||
|
||||
// GPIO
|
||||
_PAD_CFG_STRUCT(GPIO_101, 0x44000100, 0x00000000),
|
||||
|
||||
// GPIO
|
||||
_PAD_CFG_STRUCT(GPIO_102, 0x44000100, 0x00000000),
|
||||
|
||||
// *FST_SPI_CLK
|
||||
_PAD_CFG_STRUCT(GPIO_103, 0x44000400, 0x0003fc00),
|
||||
|
||||
// *n/a
|
||||
_PAD_CFG_STRUCT(FST_SPI_CLK_FB, 0x44000400, 0x0003c000),
|
||||
|
||||
// SIO_SPI_0_CLK
|
||||
_PAD_CFG_STRUCT(GPIO_104, 0x44000400, 0x0001d200),
|
||||
|
||||
// SIO_SPI_0_FS0
|
||||
_PAD_CFG_STRUCT(GPIO_105, 0x44000400, 0x0001f200),
|
||||
|
||||
// SIO_SPI_0_FS1
|
||||
_PAD_CFG_STRUCT(GPIO_106, 0x44000400, 0x0001f200),
|
||||
|
||||
// SIO_SPI_0_RXD
|
||||
_PAD_CFG_STRUCT(GPIO_109, 0x44000402, 0x0001f200),
|
||||
|
||||
// SIO_SPI_0_TXD
|
||||
_PAD_CFG_STRUCT(GPIO_110, 0x44000400, 0x0001f200),
|
||||
|
||||
// SIO_SPI_1_CLK
|
||||
_PAD_CFG_STRUCT(GPIO_111, 0x44000400, 0x00001000),
|
||||
|
||||
// SIO_SPI_1_FS0
|
||||
_PAD_CFG_STRUCT(GPIO_112, 0x44000400, 0x00001000),
|
||||
|
||||
// SIO_SPI_1_FS1
|
||||
_PAD_CFG_STRUCT(GPIO_113, 0x44000400, 0x00001000),
|
||||
|
||||
// SIO_SPI_1_RXD
|
||||
_PAD_CFG_STRUCT(GPIO_116, 0x44000402, 0x0001d000),
|
||||
|
||||
// SIO_SPI_1_TXD
|
||||
_PAD_CFG_STRUCT(GPIO_117, 0x44000400, 0x00001000),
|
||||
|
||||
// SIO_SPI_2_CLK
|
||||
_PAD_CFG_STRUCT(GPIO_118, 0x44000400, 0x00001000),
|
||||
|
||||
// SIO_SPI_2_FS0
|
||||
_PAD_CFG_STRUCT(GPIO_119, 0x44000400, 0x00001000),
|
||||
|
||||
// SIO_SPI_2_FS1
|
||||
_PAD_CFG_STRUCT(GPIO_120, 0x44000400, 0x00001000),
|
||||
|
||||
// SIO_SPI_2_FS2
|
||||
_PAD_CFG_STRUCT(GPIO_121, 0x44000400, 0x00001000),
|
||||
|
||||
// SIO_SPI_2_RXD
|
||||
_PAD_CFG_STRUCT(GPIO_122, 0x44000400, 0x00001000),
|
||||
|
||||
// SIO_SPI_2_TXD
|
||||
_PAD_CFG_STRUCT(GPIO_123, 0x44000400, 0x00001000),
|
||||
|
||||
|
||||
// *******************************
|
||||
// ******* GPIO Group West *******
|
||||
// *******************************
|
||||
// LPSS_I2C0_SDA
|
||||
_PAD_CFG_STRUCT(GPIO_124, 0x44000402, 0x00012700),
|
||||
|
||||
// LPSS_I2C0_SCL
|
||||
_PAD_CFG_STRUCT(GPIO_125, 0x44000402, 0x00012700),
|
||||
|
||||
// LPSS_I2C1_SDA
|
||||
_PAD_CFG_STRUCT(GPIO_126, 0x44000402, 0x00012700),
|
||||
|
||||
// LPSS_I2C1_SCL
|
||||
_PAD_CFG_STRUCT(GPIO_127, 0x44000402, 0x00012700),
|
||||
|
||||
// LPSS_I2C2_SDA
|
||||
_PAD_CFG_STRUCT(GPIO_128, 0x44000402, 0x00012700),
|
||||
|
||||
// LPSS_I2C2_SCL
|
||||
_PAD_CFG_STRUCT(GPIO_129, 0x44000402, 0x00012700),
|
||||
|
||||
// LPSS_I2C3_SDA
|
||||
_PAD_CFG_STRUCT(GPIO_130, 0x44000402, 0x00012700),
|
||||
|
||||
// LPSS_I2C3_SCL
|
||||
_PAD_CFG_STRUCT(GPIO_131, 0x44000402, 0x00012700),
|
||||
|
||||
// LPSS_I2C4_SDA
|
||||
_PAD_CFG_STRUCT(GPIO_132, 0x44000402, 0x00012700),
|
||||
|
||||
// LPSS_I2C4_SCL
|
||||
_PAD_CFG_STRUCT(GPIO_133, 0x44000402, 0x00012700),
|
||||
|
||||
// LPSS_I2C5_SDA
|
||||
_PAD_CFG_STRUCT(GPIO_134, 0x44000402, 0x0001f200),
|
||||
|
||||
// LPSS_I2C5_SCL
|
||||
_PAD_CFG_STRUCT(GPIO_135, 0x44000402, 0x0001f200),
|
||||
|
||||
// LPSS_I2C6_SDA
|
||||
_PAD_CFG_STRUCT(GPIO_136, 0x44000402, 0x0001f200),
|
||||
|
||||
// LPSS_I2C6_SCL
|
||||
_PAD_CFG_STRUCT(GPIO_137, 0x44000402, 0x0001f200),
|
||||
|
||||
// LPSS_I2C7_SDA
|
||||
_PAD_CFG_STRUCT(GPIO_138, 0x44000402, 0x00006700),
|
||||
|
||||
// LPSS_I2C7_SCL
|
||||
_PAD_CFG_STRUCT(GPIO_139, 0x44000402, 0x00006700),
|
||||
|
||||
// AVS_I2S6_BCLK
|
||||
_PAD_CFG_STRUCT(GPIO_146, 0x44000800, 0x0003d000),
|
||||
|
||||
// AVS_I2S6_WS_SYNC
|
||||
_PAD_CFG_STRUCT(GPIO_147, 0x44000800, 0x0003d000),
|
||||
|
||||
// AVS_I2S6_SDI
|
||||
_PAD_CFG_STRUCT(GPIO_148, 0x44000802, 0x0003d000),
|
||||
|
||||
// AVS_I2S6_SDO
|
||||
_PAD_CFG_STRUCT(GPIO_149, 0x44000800, 0x0003d000),
|
||||
|
||||
// AVS_I2S5_BCLK
|
||||
_PAD_CFG_STRUCT(GPIO_150, 0x44000800, 0x0001d200),
|
||||
|
||||
// AVS_I2S5_WS_SYNC
|
||||
_PAD_CFG_STRUCT(GPIO_151, 0x44000800, 0x0001d200),
|
||||
|
||||
// AVS_I2S5_SDI
|
||||
_PAD_CFG_STRUCT(GPIO_152, 0x44000802, 0x0001d200),
|
||||
|
||||
// AVS_I2S5_SDO
|
||||
_PAD_CFG_STRUCT(GPIO_153, 0x44000800, 0x0001c200),
|
||||
|
||||
// *GPIO
|
||||
_PAD_CFG_STRUCT(GPIO_154, 0x44000102, 0x00000000),
|
||||
|
||||
// SPKR
|
||||
_PAD_CFG_STRUCT(GPIO_155, 0x44000800, 0x0003d000),
|
||||
|
||||
// *PCIE_CLKREQ0_N
|
||||
_PAD_CFG_STRUCT(GPIO_209, 0x44000400, 0x00001000),
|
||||
|
||||
// *PCIE_CLKREQ1_N
|
||||
_PAD_CFG_STRUCT(GPIO_210, 0x44000400, 0x00001000),
|
||||
|
||||
// *PCIE_CLKREQ2_N
|
||||
_PAD_CFG_STRUCT(GPIO_211, 0x44000400, 0x00001000),
|
||||
|
||||
// *PCIE_CLKREQ3_N
|
||||
_PAD_CFG_STRUCT(GPIO_212, 0x44000400, 0x00001000),
|
||||
|
||||
// *OSC_CLK_OUT_0
|
||||
_PAD_CFG_STRUCT(OSC_CLK_OUT_0, 0x44000400, 0x00001000),
|
||||
|
||||
// *OSC_CLK_OUT_1
|
||||
_PAD_CFG_STRUCT(OSC_CLK_OUT_1, 0x44000400, 0x00001000),
|
||||
|
||||
// *OSC_CLK_OUT_2
|
||||
_PAD_CFG_STRUCT(OSC_CLK_OUT_2, 0x44000400, 0x00001000),
|
||||
|
||||
// *OSC_CLK_OUT_3
|
||||
_PAD_CFG_STRUCT(OSC_CLK_OUT_3, 0x44000400, 0x00001000),
|
||||
|
||||
// GPIO
|
||||
_PAD_CFG_STRUCT(OSC_CLK_OUT_4, 0x44000100, 0x00000000),
|
||||
|
||||
// *GPIO
|
||||
_PAD_CFG_STRUCT(PMU_AC_PRESENT, 0x44000102, 0x00000000),
|
||||
|
||||
// GPIO
|
||||
_PAD_CFG_STRUCT(PMU_BATLOW_B, 0x44000102, 0x00000000),
|
||||
|
||||
// *PMU_PLTRST_N
|
||||
_PAD_CFG_STRUCT(PMU_PLTRST_B, 0x44000400, 0x0003c000),
|
||||
|
||||
// *PMU_PWRBTN_N
|
||||
_PAD_CFG_STRUCT(PMU_PWRBTN_B, 0x44000402, 0x0003f000),
|
||||
|
||||
// *PMU_RSTBTN_N
|
||||
_PAD_CFG_STRUCT(PMU_RESETBUTTON_B, 0x44000402, 0x0003c000),
|
||||
|
||||
// *PMU_SLP_S0_N
|
||||
_PAD_CFG_STRUCT(PMU_SLP_S0_B, 0x44000400, 0x0003c000),
|
||||
|
||||
// *PMU_SLP_S3_N
|
||||
_PAD_CFG_STRUCT(PMU_SLP_S3_B, 0x44000400, 0x0003c000),
|
||||
|
||||
// *PMU_SLP_S4_N
|
||||
_PAD_CFG_STRUCT(PMU_SLP_S4_B, 0x44000400, 0x0003c000),
|
||||
|
||||
// *PMU_SUSCLK
|
||||
_PAD_CFG_STRUCT(PMU_SUSCLK, 0x44000400, 0x0003c000),
|
||||
|
||||
// *GPIO
|
||||
_PAD_CFG_STRUCT(PMU_WAKE_B, 0x44000201, 0x0003f000),
|
||||
|
||||
// *SUS_STAT_B
|
||||
_PAD_CFG_STRUCT(SUS_STAT_B, 0x44000400, 0x0003c000),
|
||||
|
||||
// GPIO
|
||||
_PAD_CFG_STRUCT(SUSPWRDNACK, 0x44000102, 0x00000000),
|
||||
|
||||
|
||||
// ************************************
|
||||
// ******* GPIO Group SouthWest *******
|
||||
// ************************************
|
||||
// PCIE_WAKE0_N
|
||||
_PAD_CFG_STRUCT(GPIO_205, 0x44000402, 0x00000000),
|
||||
|
||||
// PCIE_WAKE1_N
|
||||
_PAD_CFG_STRUCT(GPIO_206, 0x44000402, 0x00000000),
|
||||
|
||||
// PCIE_WAKE2_N
|
||||
_PAD_CFG_STRUCT(GPIO_207, 0x44000402, 0x00000000),
|
||||
|
||||
// PCIE_WAKE3_N
|
||||
_PAD_CFG_STRUCT(GPIO_208, 0x44000402, 0x00000000),
|
||||
|
||||
// *EMMC_CLK
|
||||
_PAD_CFG_STRUCT(GPIO_156, 0x44000402, 0x00005000),
|
||||
|
||||
// *EMMC_D0
|
||||
_PAD_CFG_STRUCT(GPIO_157, 0x44000402, 0x00023000),
|
||||
|
||||
// *EMMC_D1
|
||||
_PAD_CFG_STRUCT(GPIO_158, 0x44000402, 0x00023000),
|
||||
|
||||
// *EMMC_D2
|
||||
_PAD_CFG_STRUCT(GPIO_159, 0x44000402, 0x00023000),
|
||||
|
||||
// *EMMC_D3
|
||||
_PAD_CFG_STRUCT(GPIO_160, 0x44000402, 0x00023000),
|
||||
|
||||
// *EMMC_D4
|
||||
_PAD_CFG_STRUCT(GPIO_161, 0x44000402, 0x00023000),
|
||||
|
||||
// *EMMC_D5
|
||||
_PAD_CFG_STRUCT(GPIO_162, 0x44000402, 0x00023000),
|
||||
|
||||
// *EMMC_D6
|
||||
_PAD_CFG_STRUCT(GPIO_163, 0x44000402, 0x00023000),
|
||||
|
||||
// *EMMC_D7
|
||||
_PAD_CFG_STRUCT(GPIO_164, 0x44000402, 0x00023000),
|
||||
|
||||
// *EMMC_CMD
|
||||
_PAD_CFG_STRUCT(GPIO_165, 0x44000402, 0x00023000),
|
||||
|
||||
// *GPIO
|
||||
_PAD_CFG_STRUCT(GPIO_166, 0x44000300, 0x00001000),
|
||||
|
||||
// *GPIO
|
||||
_PAD_CFG_STRUCT(GPIO_167, 0x44000102, 0x00023000),
|
||||
|
||||
// *GPIO
|
||||
_PAD_CFG_STRUCT(GPIO_168, 0x44000100, 0x00023000),
|
||||
|
||||
// *GPIO
|
||||
_PAD_CFG_STRUCT(GPIO_169, 0x44000200, 0x00003000),
|
||||
|
||||
// *GPIO
|
||||
_PAD_CFG_STRUCT(GPIO_170, 0x44000201, 0x00003000),
|
||||
|
||||
// *GPIO
|
||||
_PAD_CFG_STRUCT(GPIO_171, 0x44000201, 0x00003000),
|
||||
|
||||
// SDCARD_CLK
|
||||
_PAD_CFG_STRUCT(GPIO_172, 0x44000400, 0x00021100),
|
||||
|
||||
// n/a
|
||||
_PAD_CFG_STRUCT(GPIO_179, 0x44000400, 0x00001000),
|
||||
|
||||
// SDCARD_D0
|
||||
_PAD_CFG_STRUCT(GPIO_173, 0x44000402, 0x00023100),
|
||||
|
||||
// SDCARD_D1
|
||||
_PAD_CFG_STRUCT(GPIO_174, 0x44000402, 0x00023000),
|
||||
|
||||
// SDCARD_D2
|
||||
_PAD_CFG_STRUCT(GPIO_175, 0x44000402, 0x00023000),
|
||||
|
||||
// SDCARD_D3
|
||||
_PAD_CFG_STRUCT(GPIO_176, 0x44000402, 0x00023000),
|
||||
|
||||
// SDCARD_CD_B
|
||||
_PAD_CFG_STRUCT(GPIO_177, 0x44000402, 0x00003000),
|
||||
|
||||
// SDCARD_CMD
|
||||
_PAD_CFG_STRUCT(GPIO_178, 0x44000402, 0x00023100),
|
||||
|
||||
// SDCARD_LVL_WP
|
||||
_PAD_CFG_STRUCT(GPIO_186, 0x44000402, 0x00003000),
|
||||
|
||||
// *EMMC_RCLK
|
||||
_PAD_CFG_STRUCT(GPIO_182, 0x44000400, 0x0001d000),
|
||||
|
||||
// GPIO
|
||||
_PAD_CFG_STRUCT(GPIO_183, 0x44000200, 0x00001000),
|
||||
|
||||
// SMB_ALERT_N
|
||||
_PAD_CFG_STRUCT(SMB_ALERTB, 0x44000402, 0x0003f000),
|
||||
|
||||
// SMB_CLK
|
||||
_PAD_CFG_STRUCT(SMB_CLK, 0x44000402, 0x0003f000),
|
||||
|
||||
// SMB_DATA
|
||||
_PAD_CFG_STRUCT(SMB_DATA, 0x44000402, 0x0003f000),
|
||||
|
||||
// LPC_ILB_SERIRQ
|
||||
_PAD_CFG_STRUCT(LPC_ILB_SERIRQ, 0x44000402, 0x0003f000),
|
||||
|
||||
// LPC_CLKOUT0
|
||||
_PAD_CFG_STRUCT(LPC_CLKOUT0, 0x44000400, 0x00020100),
|
||||
|
||||
// LPC_CLKOUT1
|
||||
_PAD_CFG_STRUCT(LPC_CLKOUT1, 0x44000400, 0x00020100),
|
||||
|
||||
// LPC_AD0
|
||||
_PAD_CFG_STRUCT(LPC_AD0, 0x44000402, 0x00023100),
|
||||
|
||||
// LPC_AD1
|
||||
_PAD_CFG_STRUCT(LPC_AD1, 0x44000402, 0x00023100),
|
||||
|
||||
// LPC_AD2
|
||||
_PAD_CFG_STRUCT(LPC_AD2, 0x44000402, 0x00023100),
|
||||
|
||||
// LPC_AD3
|
||||
_PAD_CFG_STRUCT(LPC_AD3, 0x44000402, 0x00023100),
|
||||
|
||||
// LPC_CLKRUNB
|
||||
_PAD_CFG_STRUCT(LPC_CLKRUNB, 0x44000400, 0x00023100),
|
||||
|
||||
// LPC_FRAMEB
|
||||
_PAD_CFG_STRUCT(LPC_FRAMEB, 0x44000400, 0x00023100),
|
||||
};
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,432 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2019 Felix Singer <felix.singer@9elements.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <string.h>
|
||||
#include <soc/ramstage.h>
|
||||
#include <fsp/api.h>
|
||||
#include <FspsUpd.h>
|
||||
#include <console/console.h>
|
||||
|
||||
void mainboard_silicon_init_params(FSP_S_CONFIG *silconfig)
|
||||
{
|
||||
printk(BIOS_DEBUG, "MAINBOARD: %s/%s called\n", __FILE__, __func__);
|
||||
|
||||
silconfig->C1e = 0x1; // 0x0
|
||||
silconfig->PkgCStateLimit = 0xFE; // 0x2
|
||||
silconfig->CStateAutoDemotion = 0x3; // 0x0
|
||||
silconfig->CStateUnDemotion = 0x3; // 0x0
|
||||
silconfig->PkgCStateDemotion = 0x1; // 0x0
|
||||
silconfig->PkgCStateUnDemotion = 0x1; // 0x0
|
||||
silconfig->IpuEn = 0x0; // 0x1
|
||||
silconfig->Pme = 0x1; // 0x0
|
||||
silconfig->HdAudioIoBufferOwnership = 0x3; // 0x0
|
||||
silconfig->DspEndpointDmic = 0x0; // 0x1
|
||||
silconfig->DspEndpointBluetooth = 0x0; // 0x1
|
||||
silconfig->DspEndpointI2sSkp = 0x1; // 0x0
|
||||
silconfig->DspEndpointI2sHp = 0x1; // 0x0
|
||||
silconfig->HDAudioPwrGate = 0x1; // 0x0
|
||||
silconfig->HDAudioClkGate = 0x1; // 0x0
|
||||
silconfig->DspFeatureMask = 0x2A; // 0x0
|
||||
silconfig->HpetBdfValid = 0x1; // 0x0
|
||||
silconfig->HpetDeviceNumber = 0xF; // 0x1f
|
||||
silconfig->IoApicBdfValid = 0x1; // 0x0
|
||||
silconfig->IoApicDeviceNumber = 0x1F; // 0xf
|
||||
silconfig->IshEnable = 0x0; // 0x1
|
||||
silconfig->SpiEiss = 0x0; // 0x1
|
||||
silconfig->LPSS_S0ixEnable = 0x1; // 0x0
|
||||
silconfig->SdcardEnabled = 0x0; // 0x1
|
||||
silconfig->eMMCHostMaxSpeed = 0x2; // 0x0
|
||||
silconfig->Usb30Mode = 0x1; // 0x0
|
||||
silconfig->VtdEnable = 0x1; // 0x0
|
||||
silconfig->MonitorMwaitEnable = 0x0; // 0x1
|
||||
silconfig->HdAudioDspUaaCompliance = 0x1; // 0x0
|
||||
silconfig->InitS3Cpu = 0x1; // 0x0
|
||||
|
||||
silconfig->PortUsb20PerPortTxPeHalf[0] = 0x0;
|
||||
silconfig->PortUsb20PerPortPeTxiSet[0] = 0x7;
|
||||
silconfig->PortUsb20PerPortTxiSet[0] = 0x0;
|
||||
silconfig->PortUsb20HsSkewSel[0] = 0x0;
|
||||
silconfig->PortUsb20IUsbTxEmphasisEn[0] = 0x3;
|
||||
silconfig->PortUsb20PerPortRXISet[0] = 0x0;
|
||||
silconfig->PortUsb20HsNpreDrvSel[0] = 0x0;
|
||||
|
||||
silconfig->PortUsb20PerPortTxPeHalf[1] = 0x0;
|
||||
silconfig->PortUsb20PerPortPeTxiSet[1] = 0x6;
|
||||
silconfig->PortUsb20PerPortTxiSet[1] = 0x0;
|
||||
silconfig->PortUsb20HsSkewSel[1] = 0x0;
|
||||
silconfig->PortUsb20IUsbTxEmphasisEn[1] = 0x3;
|
||||
silconfig->PortUsb20PerPortRXISet[1] = 0x0;
|
||||
silconfig->PortUsb20HsNpreDrvSel[1] = 0x0;
|
||||
|
||||
silconfig->PortUsb20PerPortTxPeHalf[2] = 0x0;
|
||||
silconfig->PortUsb20PerPortPeTxiSet[2] = 0x6;
|
||||
silconfig->PortUsb20PerPortTxiSet[2] = 0x0;
|
||||
silconfig->PortUsb20HsSkewSel[2] = 0x0;
|
||||
silconfig->PortUsb20IUsbTxEmphasisEn[2] = 0x3;
|
||||
silconfig->PortUsb20PerPortRXISet[2] = 0x0;
|
||||
silconfig->PortUsb20HsNpreDrvSel[2] = 0x0;
|
||||
|
||||
silconfig->PortUsb20PerPortTxPeHalf[3] = 0x0;
|
||||
silconfig->PortUsb20PerPortPeTxiSet[3] = 0x6;
|
||||
silconfig->PortUsb20PerPortTxiSet[3] = 0x0;
|
||||
silconfig->PortUsb20HsSkewSel[3] = 0x0;
|
||||
silconfig->PortUsb20IUsbTxEmphasisEn[3] = 0x3;
|
||||
silconfig->PortUsb20PerPortRXISet[3] = 0x0;
|
||||
silconfig->PortUsb20HsNpreDrvSel[3] = 0x0;
|
||||
|
||||
silconfig->PortUsb20PerPortTxPeHalf[4] = 0x0;
|
||||
silconfig->PortUsb20PerPortPeTxiSet[4] = 0x7;
|
||||
silconfig->PortUsb20PerPortTxiSet[4] = 0x0;
|
||||
silconfig->PortUsb20HsSkewSel[4] = 0x0;
|
||||
silconfig->PortUsb20IUsbTxEmphasisEn[4] = 0x3;
|
||||
silconfig->PortUsb20PerPortRXISet[4] = 0x0;
|
||||
silconfig->PortUsb20HsNpreDrvSel[4] = 0x0;
|
||||
|
||||
silconfig->PortUsb20PerPortTxPeHalf[5] = 0x0;
|
||||
silconfig->PortUsb20PerPortPeTxiSet[5] = 0x7;
|
||||
silconfig->PortUsb20PerPortTxiSet[5] = 0x0;
|
||||
silconfig->PortUsb20HsSkewSel[5] = 0x0;
|
||||
silconfig->PortUsb20IUsbTxEmphasisEn[5] = 0x3;
|
||||
silconfig->PortUsb20PerPortRXISet[5] = 0x0;
|
||||
silconfig->PortUsb20HsNpreDrvSel[5] = 0x0;
|
||||
|
||||
silconfig->PortUsb20PerPortTxPeHalf[6] = 0x0;
|
||||
silconfig->PortUsb20PerPortPeTxiSet[6] = 0x7;
|
||||
silconfig->PortUsb20PerPortTxiSet[6] = 0x0;
|
||||
silconfig->PortUsb20HsSkewSel[6] = 0x0;
|
||||
silconfig->PortUsb20IUsbTxEmphasisEn[6] = 0x3;
|
||||
silconfig->PortUsb20PerPortRXISet[6] = 0x0;
|
||||
silconfig->PortUsb20HsNpreDrvSel[6] = 0x0;
|
||||
|
||||
silconfig->PortUsb20PerPortTxPeHalf[7] = 0x0;
|
||||
silconfig->PortUsb20PerPortPeTxiSet[7] = 0x1;
|
||||
silconfig->PortUsb20PerPortTxiSet[7] = 0x3;
|
||||
silconfig->PortUsb20HsSkewSel[7] = 0x1;
|
||||
silconfig->PortUsb20IUsbTxEmphasisEn[7] = 0x1;
|
||||
silconfig->PortUsb20PerPortRXISet[7] = 0x0;
|
||||
silconfig->PortUsb20HsNpreDrvSel[7] = 0x3;
|
||||
|
||||
|
||||
silconfig->WriteProtectionEnable[0] = 0x1;
|
||||
silconfig->ReadProtectionEnable[0] = 0x1;
|
||||
silconfig->ProtectedRangeLimit[0] = 0xFFF;
|
||||
silconfig->ProtectedRangeBase[0] = 0x0;
|
||||
|
||||
silconfig->IPC[0] = 0xFFFFEEF8;
|
||||
silconfig->IPC[1] = 0xFFFFFFFF;
|
||||
silconfig->IPC[2] = 0xFFFFFFFF;
|
||||
silconfig->IPC[3] = 0xFFFFFFFF;
|
||||
|
||||
silconfig->SataPortsDisableDynamicPg[0] = 0x0;
|
||||
silconfig->SataPortsEnable[0] = 0x1;
|
||||
silconfig->SataPortsDevSlp[0] = 0x0;
|
||||
silconfig->SataPortsHotPlug[0] = 0x0;
|
||||
silconfig->SataPortsInterlockSw[0] = 0x1;
|
||||
silconfig->SataPortsExternal[0] = 0x0;
|
||||
silconfig->SataPortsSpinUp[0] = 0x0;
|
||||
silconfig->SataPortsSolidStateDrive[0] = 0x0;
|
||||
silconfig->SataPortsEnableDitoConfig[0] = 0x0;
|
||||
silconfig->SataPortsDmVal[0] = 0xF;
|
||||
silconfig->SataPortsDitoVal[0] = 0x271;
|
||||
|
||||
silconfig->SataPortsDisableDynamicPg[1] = 0x0;
|
||||
silconfig->SataPortsEnable[1] = 0x1;
|
||||
silconfig->SataPortsDevSlp[1] = 0x0;
|
||||
silconfig->SataPortsHotPlug[1] = 0x0;
|
||||
silconfig->SataPortsInterlockSw[1] = 0x1;
|
||||
silconfig->SataPortsExternal[1] = 0x0;
|
||||
silconfig->SataPortsSpinUp[1] = 0x0;
|
||||
silconfig->SataPortsSolidStateDrive[1] = 0x0;
|
||||
silconfig->SataPortsEnableDitoConfig[1] = 0x0;
|
||||
silconfig->SataPortsDmVal[1] = 0xF;
|
||||
silconfig->SataPortsDitoVal[1] = 0x271;
|
||||
|
||||
|
||||
silconfig->PcieRootPortEn[0] = 0x1;
|
||||
silconfig->PcieRpHide[0] = 0x0;
|
||||
silconfig->PcieRpSlotImplemented[0] = 0x1;
|
||||
silconfig->PcieRpHotPlug[0] = 0x0;
|
||||
silconfig->PcieRpPmSci[0] = 0x1;
|
||||
silconfig->PcieRpExtSync[0] = 0x1;
|
||||
silconfig->PcieRpTransmitterHalfSwing[0] = 0x0;
|
||||
silconfig->PcieRpAcsEnabled[0] = 0x1;
|
||||
silconfig->PcieRpClkReqSupported[0] = 0x1;
|
||||
silconfig->PcieRpClkReqNumber[0] = 0x2;
|
||||
silconfig->PcieRpClkReqDetect[0] = 0x0;
|
||||
silconfig->AdvancedErrorReporting[0] = 0x0;
|
||||
silconfig->PmeInterrupt[0] = 0x0;
|
||||
silconfig->UnsupportedRequestReport[0] = 0x0;
|
||||
silconfig->FatalErrorReport[0] = 0x0;
|
||||
silconfig->NoFatalErrorReport[0] = 0x0;
|
||||
silconfig->CorrectableErrorReport[0] = 0x0;
|
||||
silconfig->SystemErrorOnFatalError[0] = 0x0;
|
||||
silconfig->SystemErrorOnNonFatalError[0] = 0x0;
|
||||
silconfig->SystemErrorOnCorrectableError[0] = 0x0;
|
||||
silconfig->PcieRpSpeed[0] = 0x0;
|
||||
silconfig->PhysicalSlotNumber[0] = 0x0;
|
||||
silconfig->PcieRpCompletionTimeout[0] = 0x0;
|
||||
silconfig->PtmEnable[0] = 0x0;
|
||||
silconfig->PcieRpAspm[0] = 0x4;
|
||||
silconfig->PcieRpL1Substates[0] = 0x3;
|
||||
silconfig->PcieRpLtrEnable[0] = 0x1;
|
||||
silconfig->PcieRpLtrConfigLock[0] = 0x0;
|
||||
silconfig->PcieRpSelectableDeemphasis[0] = 0x1;
|
||||
silconfig->PcieRpNonSnoopLatencyOverrideValue[0] = 0x3C;
|
||||
silconfig->PcieRpNonSnoopLatencyOverrideMultiplier[0] = 0x2;
|
||||
silconfig->PcieRpSlotPowerLimitScale[0] = 0x0;
|
||||
silconfig->PcieRpSlotPowerLimitValue[0] = 0x0;
|
||||
silconfig->PcieRpLtrMaxNonSnoopLatency[0] = 0x1003;
|
||||
silconfig->PcieRpNonSnoopLatencyOverrideMode[0] = 0x2;
|
||||
silconfig->PcieRpLtrMaxSnoopLatency[0] = 0x1003;
|
||||
silconfig->PcieRpSnoopLatencyOverrideMode[0] = 0x2;
|
||||
silconfig->PcieRpSnoopLatencyOverrideValue[0] = 0x3C;
|
||||
silconfig->PcieRpSnoopLatencyOverrideMultiplier[0] = 0x2;
|
||||
|
||||
silconfig->PcieRootPortEn[1] = 0x1;
|
||||
silconfig->PcieRpHide[1] = 0x0;
|
||||
silconfig->PcieRpSlotImplemented[1] = 0x1;
|
||||
silconfig->PcieRpHotPlug[1] = 0x0;
|
||||
silconfig->PcieRpPmSci[1] = 0x1;
|
||||
silconfig->PcieRpExtSync[1] = 0x1;
|
||||
silconfig->PcieRpTransmitterHalfSwing[1] = 0x0;
|
||||
silconfig->PcieRpAcsEnabled[1] = 0x1;
|
||||
silconfig->PcieRpClkReqSupported[1] = 0x1;
|
||||
silconfig->PcieRpClkReqNumber[1] = 0x3;
|
||||
silconfig->PcieRpClkReqDetect[1] = 0x0;
|
||||
silconfig->AdvancedErrorReporting[1] = 0x0;
|
||||
silconfig->PmeInterrupt[1] = 0x0;
|
||||
silconfig->UnsupportedRequestReport[1] = 0x0;
|
||||
silconfig->FatalErrorReport[1] = 0x0;
|
||||
silconfig->NoFatalErrorReport[1] = 0x0;
|
||||
silconfig->CorrectableErrorReport[1] = 0x0;
|
||||
silconfig->SystemErrorOnFatalError[1] = 0x0;
|
||||
silconfig->SystemErrorOnNonFatalError[1] = 0x0;
|
||||
silconfig->SystemErrorOnCorrectableError[1] = 0x0;
|
||||
silconfig->PcieRpSpeed[1] = 0x0;
|
||||
silconfig->PhysicalSlotNumber[1] = 0x1;
|
||||
silconfig->PcieRpCompletionTimeout[1] = 0x0;
|
||||
silconfig->PtmEnable[1] = 0x0;
|
||||
silconfig->PcieRpAspm[1] = 0x4;
|
||||
silconfig->PcieRpL1Substates[1] = 0x3;
|
||||
silconfig->PcieRpLtrEnable[1] = 0x1;
|
||||
silconfig->PcieRpLtrConfigLock[1] = 0x0;
|
||||
silconfig->PcieRpSelectableDeemphasis[1] = 0x1;
|
||||
silconfig->PcieRpNonSnoopLatencyOverrideValue[1] = 0x3C;
|
||||
silconfig->PcieRpNonSnoopLatencyOverrideMultiplier[1] = 0x2;
|
||||
silconfig->PcieRpSlotPowerLimitScale[1] = 0x0;
|
||||
silconfig->PcieRpSlotPowerLimitValue[1] = 0x0;
|
||||
silconfig->PcieRpLtrMaxNonSnoopLatency[1] = 0x1003;
|
||||
silconfig->PcieRpNonSnoopLatencyOverrideMode[1] = 0x2;
|
||||
silconfig->PcieRpLtrMaxSnoopLatency[1] = 0x1003;
|
||||
silconfig->PcieRpSnoopLatencyOverrideMode[1] = 0x2;
|
||||
silconfig->PcieRpSnoopLatencyOverrideValue[1] = 0x3C;
|
||||
silconfig->PcieRpSnoopLatencyOverrideMultiplier[1] = 0x2;
|
||||
|
||||
silconfig->PcieRootPortEn[2] = 0x1;
|
||||
silconfig->PcieRpHide[2] = 0x0;
|
||||
silconfig->PcieRpSlotImplemented[2] = 0x1;
|
||||
silconfig->PcieRpHotPlug[2] = 0x0;
|
||||
silconfig->PcieRpPmSci[2] = 0x1;
|
||||
silconfig->PcieRpExtSync[2] = 0x1;
|
||||
silconfig->PcieRpTransmitterHalfSwing[2] = 0x0;
|
||||
silconfig->PcieRpAcsEnabled[2] = 0x1;
|
||||
silconfig->PcieRpClkReqSupported[2] = 0x1;
|
||||
silconfig->PcieRpClkReqNumber[2] = 0x0;
|
||||
silconfig->PcieRpClkReqDetect[2] = 0x0;
|
||||
silconfig->AdvancedErrorReporting[2] = 0x0;
|
||||
silconfig->PmeInterrupt[2] = 0x0;
|
||||
silconfig->UnsupportedRequestReport[2] = 0x0;
|
||||
silconfig->FatalErrorReport[2] = 0x0;
|
||||
silconfig->NoFatalErrorReport[2] = 0x0;
|
||||
silconfig->CorrectableErrorReport[2] = 0x0;
|
||||
silconfig->SystemErrorOnFatalError[2] = 0x0;
|
||||
silconfig->SystemErrorOnNonFatalError[2] = 0x0;
|
||||
silconfig->SystemErrorOnCorrectableError[2] = 0x0;
|
||||
silconfig->PcieRpSpeed[2] = 0x0;
|
||||
silconfig->PhysicalSlotNumber[2] = 0x2;
|
||||
silconfig->PcieRpCompletionTimeout[2] = 0x0;
|
||||
silconfig->PtmEnable[2] = 0x0;
|
||||
silconfig->PcieRpAspm[2] = 0x4;
|
||||
silconfig->PcieRpL1Substates[2] = 0x3;
|
||||
silconfig->PcieRpLtrEnable[2] = 0x1;
|
||||
silconfig->PcieRpLtrConfigLock[2] = 0x0;
|
||||
silconfig->PcieRpSelectableDeemphasis[2] = 0x1;
|
||||
silconfig->PcieRpNonSnoopLatencyOverrideValue[2] = 0x3C;
|
||||
silconfig->PcieRpNonSnoopLatencyOverrideMultiplier[2] = 0x2;
|
||||
silconfig->PcieRpSlotPowerLimitScale[2] = 0x0;
|
||||
silconfig->PcieRpSlotPowerLimitValue[2] = 0x0;
|
||||
silconfig->PcieRpLtrMaxNonSnoopLatency[2] = 0x1003;
|
||||
silconfig->PcieRpNonSnoopLatencyOverrideMode[2] = 0x2;
|
||||
silconfig->PcieRpLtrMaxSnoopLatency[2] = 0x1003;
|
||||
silconfig->PcieRpSnoopLatencyOverrideMode[2] = 0x2;
|
||||
silconfig->PcieRpSnoopLatencyOverrideValue[2] = 0x0;
|
||||
silconfig->PcieRpSnoopLatencyOverrideMultiplier[2] = 0x2;
|
||||
|
||||
silconfig->PcieRootPortEn[3] = 0x1;
|
||||
silconfig->PcieRpHide[3] = 0x0;
|
||||
silconfig->PcieRpSlotImplemented[3] = 0x1;
|
||||
silconfig->PcieRpHotPlug[3] = 0x0;
|
||||
silconfig->PcieRpPmSci[3] = 0x1;
|
||||
silconfig->PcieRpExtSync[3] = 0x1;
|
||||
silconfig->PcieRpTransmitterHalfSwing[3] = 0x0;
|
||||
silconfig->PcieRpAcsEnabled[3] = 0x1;
|
||||
silconfig->PcieRpClkReqSupported[3] = 0x1;
|
||||
silconfig->PcieRpClkReqNumber[3] = 0x1;
|
||||
silconfig->PcieRpClkReqDetect[3] = 0x0;
|
||||
silconfig->AdvancedErrorReporting[3] = 0x0;
|
||||
silconfig->PmeInterrupt[3] = 0x0;
|
||||
silconfig->UnsupportedRequestReport[3] = 0x0;
|
||||
silconfig->FatalErrorReport[3] = 0x0;
|
||||
silconfig->NoFatalErrorReport[3] = 0x0;
|
||||
silconfig->CorrectableErrorReport[3] = 0x0;
|
||||
silconfig->SystemErrorOnFatalError[3] = 0x0;
|
||||
silconfig->SystemErrorOnNonFatalError[3] = 0x0;
|
||||
silconfig->SystemErrorOnCorrectableError[3] = 0x0;
|
||||
silconfig->PcieRpSpeed[3] = 0x0;
|
||||
silconfig->PhysicalSlotNumber[3] = 0x3;
|
||||
silconfig->PcieRpCompletionTimeout[3] = 0x0;
|
||||
silconfig->PtmEnable[3] = 0x0;
|
||||
silconfig->PcieRpAspm[3] = 0x4;
|
||||
silconfig->PcieRpL1Substates[3] = 0x3;
|
||||
silconfig->PcieRpLtrEnable[3] = 0x1;
|
||||
silconfig->PcieRpLtrConfigLock[3] = 0x0;
|
||||
silconfig->PcieRpSelectableDeemphasis[3] = 0x1;
|
||||
silconfig->PcieRpNonSnoopLatencyOverrideValue[3] = 0x3C;
|
||||
silconfig->PcieRpNonSnoopLatencyOverrideMultiplier[3] = 0x2;
|
||||
silconfig->PcieRpSlotPowerLimitScale[3] = 0x0;
|
||||
silconfig->PcieRpSlotPowerLimitValue[3] = 0x0;
|
||||
silconfig->PcieRpLtrMaxNonSnoopLatency[3] = 0x1003;
|
||||
silconfig->PcieRpNonSnoopLatencyOverrideMode[3] = 0x2;
|
||||
silconfig->PcieRpLtrMaxSnoopLatency[3] = 0x1003;
|
||||
silconfig->PcieRpSnoopLatencyOverrideMode[3] = 0x2;
|
||||
silconfig->PcieRpSnoopLatencyOverrideValue[3] = 0x3C;
|
||||
silconfig->PcieRpSnoopLatencyOverrideMultiplier[3] = 0x2;
|
||||
|
||||
silconfig->PcieRootPortEn[4] = 0x1;
|
||||
silconfig->PcieRpHide[4] = 0x0;
|
||||
silconfig->PcieRpSlotImplemented[4] = 0x1;
|
||||
silconfig->PcieRpHotPlug[4] = 0x0;
|
||||
silconfig->PcieRpPmSci[4] = 0x1;
|
||||
silconfig->PcieRpExtSync[4] = 0x1;
|
||||
silconfig->PcieRpTransmitterHalfSwing[4] = 0x0;
|
||||
silconfig->PcieRpAcsEnabled[4] = 0x1;
|
||||
silconfig->PcieRpClkReqSupported[4] = 0x1;
|
||||
silconfig->PcieRpClkReqNumber[4] = 0x2;
|
||||
silconfig->PcieRpClkReqDetect[4] = 0x0;
|
||||
silconfig->AdvancedErrorReporting[4] = 0x0;
|
||||
silconfig->PmeInterrupt[4] = 0x0;
|
||||
silconfig->UnsupportedRequestReport[4] = 0x0;
|
||||
silconfig->FatalErrorReport[4] = 0x0;
|
||||
silconfig->NoFatalErrorReport[4] = 0x0;
|
||||
silconfig->CorrectableErrorReport[4] = 0x0;
|
||||
silconfig->SystemErrorOnFatalError[4] = 0x0;
|
||||
silconfig->SystemErrorOnNonFatalError[4] = 0x0;
|
||||
silconfig->SystemErrorOnCorrectableError[4] = 0x0;
|
||||
silconfig->PcieRpSpeed[4] = 0x0;
|
||||
silconfig->PhysicalSlotNumber[4] = 0x4;
|
||||
silconfig->PcieRpCompletionTimeout[4] = 0x0;
|
||||
silconfig->PtmEnable[4] = 0x0;
|
||||
silconfig->PcieRpAspm[4] = 0x4;
|
||||
silconfig->PcieRpL1Substates[4] = 0x3;
|
||||
silconfig->PcieRpLtrEnable[4] = 0x1;
|
||||
silconfig->PcieRpLtrConfigLock[4] = 0x0;
|
||||
silconfig->PcieRpSelectableDeemphasis[4] = 0x1;
|
||||
silconfig->PcieRpNonSnoopLatencyOverrideValue[4] = 0x3C;
|
||||
silconfig->PcieRpNonSnoopLatencyOverrideMultiplier[4] = 0x2;
|
||||
silconfig->PcieRpSlotPowerLimitScale[4] = 0x0;
|
||||
silconfig->PcieRpSlotPowerLimitValue[4] = 0x0;
|
||||
silconfig->PcieRpLtrMaxNonSnoopLatency[4] = 0x1003;
|
||||
silconfig->PcieRpNonSnoopLatencyOverrideMode[4] = 0x2;
|
||||
silconfig->PcieRpLtrMaxSnoopLatency[4] = 0x1003;
|
||||
silconfig->PcieRpSnoopLatencyOverrideMode[4] = 0x2;
|
||||
silconfig->PcieRpSnoopLatencyOverrideValue[4] = 0x3C;
|
||||
silconfig->PcieRpSnoopLatencyOverrideMultiplier[4] = 0x2;
|
||||
|
||||
silconfig->PcieRootPortEn[5] = 0x1;
|
||||
silconfig->PcieRpHide[5] = 0x0;
|
||||
silconfig->PcieRpSlotImplemented[5] = 0x1;
|
||||
silconfig->PcieRpHotPlug[5] = 0x0;
|
||||
silconfig->PcieRpPmSci[5] = 0x1;
|
||||
silconfig->PcieRpExtSync[5] = 0x1;
|
||||
silconfig->PcieRpTransmitterHalfSwing[5] = 0x0;
|
||||
silconfig->PcieRpAcsEnabled[5] = 0x1;
|
||||
silconfig->PcieRpClkReqSupported[5] = 0x1;
|
||||
silconfig->PcieRpClkReqNumber[5] = 0x3;
|
||||
silconfig->PcieRpClkReqDetect[5] = 0x0;
|
||||
silconfig->AdvancedErrorReporting[5] = 0x0;
|
||||
silconfig->PmeInterrupt[5] = 0x0;
|
||||
silconfig->UnsupportedRequestReport[5] = 0x0;
|
||||
silconfig->FatalErrorReport[5] = 0x0;
|
||||
silconfig->NoFatalErrorReport[5] = 0x0;
|
||||
silconfig->CorrectableErrorReport[5] = 0x0;
|
||||
silconfig->SystemErrorOnFatalError[5] = 0x0;
|
||||
silconfig->SystemErrorOnNonFatalError[5] = 0x0;
|
||||
silconfig->SystemErrorOnCorrectableError[5] = 0x0;
|
||||
silconfig->PcieRpSpeed[5] = 0x0;
|
||||
silconfig->PhysicalSlotNumber[5] = 0x5;
|
||||
silconfig->PcieRpCompletionTimeout[5] = 0x0;
|
||||
silconfig->PtmEnable[5] = 0x0;
|
||||
silconfig->PcieRpAspm[5] = 0x4;
|
||||
silconfig->PcieRpL1Substates[5] = 0x3;
|
||||
silconfig->PcieRpLtrEnable[5] = 0x1;
|
||||
silconfig->PcieRpLtrConfigLock[5] = 0x0;
|
||||
silconfig->PcieRpSelectableDeemphasis[5] = 0x1;
|
||||
silconfig->PcieRpNonSnoopLatencyOverrideValue[5] = 0x3C;
|
||||
silconfig->PcieRpNonSnoopLatencyOverrideMultiplier[5] = 0x2;
|
||||
silconfig->PcieRpSlotPowerLimitScale[5] = 0x0;
|
||||
silconfig->PcieRpSlotPowerLimitValue[5] = 0x0;
|
||||
silconfig->PcieRpLtrMaxNonSnoopLatency[5] = 0x1003;
|
||||
silconfig->PcieRpNonSnoopLatencyOverrideMode[5] = 0x2;
|
||||
silconfig->PcieRpLtrMaxSnoopLatency[5] = 0x1003;
|
||||
silconfig->PcieRpSnoopLatencyOverrideMode[5] = 0x2;
|
||||
silconfig->PcieRpSnoopLatencyOverrideValue[5] = 0x3C;
|
||||
silconfig->PcieRpSnoopLatencyOverrideMultiplier[5] = 0x2;
|
||||
|
||||
|
||||
silconfig->SsicRate[0] = 0x1;
|
||||
silconfig->SsicPortEnable[0] = 0x0;
|
||||
silconfig->SsicRate[1] = 0x1;
|
||||
silconfig->SsicPortEnable[1] = 0x0;
|
||||
|
||||
silconfig->PortUsb30Enable[0] = 0x1;
|
||||
silconfig->PortUs30bOverCurrentPin[0] = 0x0;
|
||||
silconfig->PortUsb30Enable[1] = 0x1;
|
||||
silconfig->PortUs30bOverCurrentPin[1] = 0x1;
|
||||
silconfig->PortUsb30Enable[2] = 0x1;
|
||||
silconfig->PortUs30bOverCurrentPin[2] = 0x1;
|
||||
silconfig->PortUsb30Enable[3] = 0x1;
|
||||
silconfig->PortUs30bOverCurrentPin[3] = 0x1;
|
||||
silconfig->PortUsb30Enable[4] = 0x1;
|
||||
silconfig->PortUs30bOverCurrentPin[4] = 0x1;
|
||||
silconfig->PortUsb30Enable[5] = 0x1;
|
||||
silconfig->PortUs30bOverCurrentPin[5] = 0x1;
|
||||
|
||||
silconfig->PortUsb20Enable[0] = 0x1;
|
||||
silconfig->PortUs20bOverCurrentPin[0] = 0x0;
|
||||
silconfig->PortUsb20Enable[1] = 0x1;
|
||||
silconfig->PortUs20bOverCurrentPin[1] = 0x1;
|
||||
silconfig->PortUsb20Enable[2] = 0x1;
|
||||
silconfig->PortUs20bOverCurrentPin[2] = 0x1;
|
||||
silconfig->PortUsb20Enable[3] = 0x1;
|
||||
silconfig->PortUs20bOverCurrentPin[3] = 0x1;
|
||||
silconfig->PortUsb20Enable[4] = 0x1;
|
||||
silconfig->PortUs20bOverCurrentPin[4] = 0x1;
|
||||
silconfig->PortUsb20Enable[5] = 0x1;
|
||||
silconfig->PortUs20bOverCurrentPin[5] = 0x1;
|
||||
silconfig->PortUsb20Enable[6] = 0x1;
|
||||
silconfig->PortUs20bOverCurrentPin[6] = 0x2;
|
||||
silconfig->PortUsb20Enable[7] = 0x1;
|
||||
silconfig->PortUs20bOverCurrentPin[7] = 0x2;
|
||||
}
|
||||
|
|
@ -0,0 +1,96 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2019 Felix Singer <felix.singer@9elements.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <string.h>
|
||||
#include <soc/romstage.h>
|
||||
#include <fsp/api.h>
|
||||
#include <FspmUpd.h>
|
||||
#include <console/console.h>
|
||||
#include "gpio.h"
|
||||
|
||||
static const uint8_t ch0_bit_swizzling[] = {
|
||||
0x0D, 0x0A, 0x08, 0x0B, 0x0C, 0x0F, 0x0E, 0x09,
|
||||
0x06, 0x00, 0x03, 0x04, 0x07, 0x01, 0x05, 0x02,
|
||||
0x1C, 0x1A, 0x19, 0x1B, 0x1D, 0x1F, 0x1E, 0x18,
|
||||
0x10, 0x17, 0x15, 0x16, 0x14, 0x12, 0x13, 0x11
|
||||
};
|
||||
|
||||
static const uint8_t ch1_bit_swizzling[] = {
|
||||
0x00, 0x07, 0x04, 0x05, 0x06, 0x02, 0x03, 0x01,
|
||||
0x08, 0x0F, 0x0D, 0x0B, 0x0A, 0x09, 0x0E, 0x0C,
|
||||
0x17, 0x11, 0x13, 0x12, 0x14, 0x15, 0x16, 0x10,
|
||||
0x1C, 0x1A, 0x1D, 0x1F, 0x18, 0x19, 0x1E, 0x1B
|
||||
};
|
||||
|
||||
static const uint8_t ch2_bit_swizzling[] = {
|
||||
0x0D, 0x08, 0x0B, 0x0E, 0x0C, 0x0F, 0x09, 0x0A,
|
||||
0x04, 0x07, 0x01, 0x06, 0x02, 0x03, 0x00, 0x05,
|
||||
0x18, 0x19, 0x1C, 0x1A, 0x1D, 0x1E, 0x1F, 0x1B,
|
||||
0x11, 0x13, 0x15, 0x10, 0x16, 0x12, 0x17, 0x14
|
||||
};
|
||||
|
||||
static const uint8_t ch3_bit_swizzling[] = {
|
||||
0x00, 0x05, 0x04, 0x07, 0x03, 0x02, 0x06, 0x01,
|
||||
0x0A, 0x0B, 0x08, 0x09, 0x0C, 0x0E, 0x0D, 0x0F,
|
||||
0x12, 0x16, 0x14, 0x13, 0x17, 0x11, 0x15, 0x10,
|
||||
0x19, 0x1F, 0x1D, 0x1B, 0x1E, 0x18, 0x1C, 0x1A
|
||||
};
|
||||
|
||||
|
||||
void mainboard_memory_init_params(FSPM_UPD *memupd)
|
||||
{
|
||||
printk(BIOS_DEBUG, "MAINBOARD: %s/%s called\n", __FILE__, __func__);
|
||||
|
||||
gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
|
||||
|
||||
memupd->FspmConfig.Package = 0x1; // 0x0
|
||||
memupd->FspmConfig.Profile = 0xB; // 0x19
|
||||
memupd->FspmConfig.MemoryDown = 0x1; // 0x0
|
||||
memupd->FspmConfig.DDR3LPageSize = 0x0; // 0x1
|
||||
memupd->FspmConfig.DIMM0SPDAddress = 0x0; // 0xa0
|
||||
memupd->FspmConfig.DIMM1SPDAddress = 0x0; // 0xa4
|
||||
memupd->FspmConfig.RmtCheckRun = 0x3; // 0x0
|
||||
memupd->FspmConfig.RmtMarginCheckScaleHighThreshold = 0xC8; // 0x0
|
||||
memupd->FspmConfig.EnhancePort8xhDecoding = 0x0; // 0x1
|
||||
memupd->FspmConfig.NpkEn = 0x0; // 0x3
|
||||
memupd->FspmConfig.PrimaryVideoAdaptor = 0x2; // 0x0
|
||||
|
||||
memupd->FspmConfig.Ch0_RankEnable = 0x1; // 0x0
|
||||
memupd->FspmConfig.Ch0_DeviceWidth = 0x1; // 0x0
|
||||
memupd->FspmConfig.Ch0_DramDensity = 0x2; // 0x0
|
||||
memupd->FspmConfig.Ch0_Option = 0x3; // 0x0
|
||||
memupd->FspmConfig.Ch1_RankEnable = 0x1; // 0x0
|
||||
memupd->FspmConfig.Ch1_DeviceWidth = 0x1; // 0x0
|
||||
memupd->FspmConfig.Ch1_DramDensity = 0x2; // 0x0
|
||||
memupd->FspmConfig.Ch1_Option = 0x3; // 0x0
|
||||
memupd->FspmConfig.Ch2_RankEnable = 0x1; // 0x0
|
||||
memupd->FspmConfig.Ch2_DeviceWidth = 0x1; // 0x0
|
||||
memupd->FspmConfig.Ch2_DramDensity = 0x2; // 0x0
|
||||
memupd->FspmConfig.Ch2_Option = 0x3; // 0x0
|
||||
memupd->FspmConfig.Ch3_RankEnable = 0x1; // 0x0
|
||||
memupd->FspmConfig.Ch3_DeviceWidth = 0x1; // 0x0
|
||||
memupd->FspmConfig.Ch3_DramDensity = 0x2; // 0x0
|
||||
memupd->FspmConfig.Ch3_Option = 0x3; // 0x0
|
||||
memupd->FspmConfig.StartTimerTickerOfPfetAssert = 0x4E20; // 0x0
|
||||
|
||||
memcpy(memupd->FspmConfig.Ch0_Bit_swizzling, &ch0_bit_swizzling,
|
||||
sizeof(ch0_bit_swizzling));
|
||||
memcpy(memupd->FspmConfig.Ch1_Bit_swizzling, &ch1_bit_swizzling,
|
||||
sizeof(ch1_bit_swizzling));
|
||||
memcpy(memupd->FspmConfig.Ch2_Bit_swizzling, &ch2_bit_swizzling,
|
||||
sizeof(ch2_bit_swizzling));
|
||||
memcpy(memupd->FspmConfig.Ch3_Bit_swizzling, &ch3_bit_swizzling,
|
||||
sizeof(ch3_bit_swizzling));
|
||||
}
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
FLASH 16M {
|
||||
SI_DESC@0x0 0x1000
|
||||
SI_BIOS@0x1000 0xefe000 {
|
||||
IFWI@0x0 0x2ff000
|
||||
OBB@0x2ff000 0xbff000 {
|
||||
FMAP@0x0 0x800
|
||||
UNIFIED_MRC_CACHE@0x800 0x21000 {
|
||||
RECOVERY_MRC_CACHE@0x0 0x10000
|
||||
RW_MRC_CACHE@0x10000 0x10000
|
||||
RW_VAR_MRC_CACHE@0x20000 0x1000
|
||||
}
|
||||
CONSOLE@0x21800 0x20000
|
||||
COREBOOT(CBFS)@0x41800 0xb7d800
|
||||
BIOS_UNUSABLE@0xbbf000 0x40000
|
||||
}
|
||||
}
|
||||
SI_DEVICEEXT@0xeff000 0x101000 {
|
||||
DEVICE_EXTENSION@0x0 0x100000
|
||||
UNUSED_HOLE@0x100000 0x1000
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,35 @@
|
|||
FLASH 16M {
|
||||
SI_DESC@0x0 0x1000
|
||||
SI_BIOS@0x1000 0xefe000 {
|
||||
WP_RO@0x0 0xe91000 {
|
||||
IFWI@0x0 0x2ff000
|
||||
FMAP@0x2ff000 0x800
|
||||
RO_VPD(PRESERVE)@0x2ff800 0x4000
|
||||
RO_SECTION@0x303800 0xb8d800 {
|
||||
RO_FRID@0x0 0x40
|
||||
RO_FRID_PAD@0x40 0x7c0
|
||||
GBB@0x800 0x40000
|
||||
COREBOOT(CBFS)@0x40800 0xb4d000
|
||||
}
|
||||
}
|
||||
MISC_RW@0xe91000 0x2d000 {
|
||||
UNIFIED_MRC_CACHE@0x0 0x21000 {
|
||||
RECOVERY_MRC_CACHE@0x0 0x10000
|
||||
RW_MRC_CACHE@0x10000 0x10000
|
||||
RW_VAR_MRC_CACHE@0x20000 0x1000
|
||||
}
|
||||
RW_SHARED@0x21000 0x4000 {
|
||||
SHARED_DATA@0x0 0x2000
|
||||
VBLOCK_DEV@0x2000 0x2000
|
||||
}
|
||||
RW_VPD(PRESERVE)@0x25000 0x2000
|
||||
RW_NVRAM(PRESERVE)@0x27000 0x5000
|
||||
FPF_STATUS@0x2c000 0x1000
|
||||
}
|
||||
BIOS_UNUSABLE@0xebe000 0x40000
|
||||
}
|
||||
SI_DEVICEEXT@0xeff000 0x101000 {
|
||||
DEVICE_EXTENSION@0x0 0x100000
|
||||
UNUSED_HOLE@0x100000 0x1000
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,40 @@
|
|||
FLASH 16M {
|
||||
SI_DESC@0x0 0x1000
|
||||
SI_BIOS@0x1000 0xefe000 {
|
||||
WP_RO@0x0 0x502000 {
|
||||
IFWI@0x0 0x2ff000
|
||||
FMAP@0x2ff000 0x800
|
||||
RO_VPD(PRESERVE)@0x2ff800 0x4000
|
||||
RO_SECTION@0x303800 0x1fe800 {
|
||||
RO_FRID@0x0 0x40
|
||||
RO_FRID_PAD@0x40 0x7c0
|
||||
GBB@0x800 0x40000
|
||||
COREBOOT(CBFS)@0x40800 0x1be000
|
||||
}
|
||||
}
|
||||
MISC_RW@0x502000 0x2d000 {
|
||||
UNIFIED_MRC_CACHE@0x0 0x21000 {
|
||||
RECOVERY_MRC_CACHE@0x0 0x10000
|
||||
RW_MRC_CACHE@0x10000 0x10000
|
||||
RW_VAR_MRC_CACHE@0x20000 0x1000
|
||||
}
|
||||
RW_SHARED@0x21000 0x4000 {
|
||||
SHARED_DATA@0x0 0x2000
|
||||
VBLOCK_DEV@0x2000 0x2000
|
||||
}
|
||||
RW_VPD(PRESERVE)@0x25000 0x2000
|
||||
RW_NVRAM(PRESERVE)@0x27000 0x5000
|
||||
FPF_STATUS@0x2c000 0x1000
|
||||
}
|
||||
RW_SECTION_A@0x52f000 0x98f000 {
|
||||
VBLOCK_A@0x0 0x10000
|
||||
FW_MAIN_A(CBFS)@0x10000 0x97efc0
|
||||
RW_FWID_A@0x98efc0 0x40
|
||||
}
|
||||
BIOS_UNUSABLE@0xebe000 0x40000
|
||||
}
|
||||
SI_DEVICEEXT@0xeff000 0x101000 {
|
||||
DEVICE_EXTENSION@0x0 0x100000
|
||||
UNUSED_HOLE@0x100000 0x1000
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,45 @@
|
|||
FLASH 16M {
|
||||
SI_DESC@0x0 0x1000
|
||||
SI_BIOS@0x1000 0xefe000 {
|
||||
WP_RO@0x0 0x503000 {
|
||||
IFWI@0x0 0x2ff000
|
||||
FMAP@0x2ff000 0x800
|
||||
RO_VPD(PRESERVE)@0x2ff800 0x4000
|
||||
RO_SECTION@0x303800 0x1ff800 {
|
||||
RO_FRID@0x0 0x40
|
||||
RO_FRID_PAD@0x40 0x7c0
|
||||
GBB@0x800 0x40000
|
||||
COREBOOT(CBFS)@0x40800 0x1bf000
|
||||
}
|
||||
}
|
||||
MISC_RW@0x503000 0x2d000 {
|
||||
UNIFIED_MRC_CACHE@0x0 0x21000 {
|
||||
RECOVERY_MRC_CACHE@0x0 0x10000
|
||||
RW_MRC_CACHE@0x10000 0x10000
|
||||
RW_VAR_MRC_CACHE@0x20000 0x1000
|
||||
}
|
||||
RW_SHARED@0x21000 0x4000 {
|
||||
SHARED_DATA@0x0 0x2000
|
||||
VBLOCK_DEV@0x2000 0x2000
|
||||
}
|
||||
RW_VPD(PRESERVE)@0x25000 0x2000
|
||||
RW_NVRAM(PRESERVE)@0x27000 0x5000
|
||||
FPF_STATUS@0x2c000 0x1000
|
||||
}
|
||||
RW_SECTION_A@0x530000 0x4c7000 {
|
||||
VBLOCK_A@0x0 0x10000
|
||||
FW_MAIN_A(CBFS)@0x10000 0x4b6fc0
|
||||
RW_FWID_A@0x4c6fc0 0x40
|
||||
}
|
||||
RW_SECTION_B@0x9f7000 0x4c7000 {
|
||||
VBLOCK_B@0x0 0x10000
|
||||
FW_MAIN_B(CBFS)@0x10000 0x4b6fc0
|
||||
RW_FWID_B@0x4c6fc0 0x40
|
||||
}
|
||||
BIOS_UNUSABLE@0xebe000 0x40000
|
||||
}
|
||||
SI_DEVICEEXT@0xeff000 0x101000 {
|
||||
DEVICE_EXTENSION@0x0 0x100000
|
||||
UNUSED_HOLE@0x100000 0x1000
|
||||
}
|
||||
}
|
||||
Loading…
Reference in New Issue