mb/intel/icelake_rvp: Add ICL U and Y RVP DIMM configuration
List of ICL board variants
1. ICL-U
DDR4 - All possible DDR4 memory type
LPDDR4 - Memory down fixed DIMM configuration
2. ICL-Y
All LPDDR4 DIMM on platform
This patch ensures to have all proper SPD configuration.
Change-Id: Id596a3c85b13559b3002dcadfee9c945256e28e7
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/29770
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
This commit is contained in:
Aamir Bohra
Subrata Banik
parent
2fd2923aeb
commit
4041bcf629
6 changed files with 212 additions and 24 deletions
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@ -22,9 +22,11 @@ verstage-$(CONFIG_CHROMEOS) += chromeos.c
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romstage-$(CONFIG_CHROMEOS) += chromeos.c
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romstage-y += romstage_fsp_params.c
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romstage-y += board_id.c
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ramstage-$(CONFIG_CHROMEOS) += chromeos.c
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ramstage-y += mainboard.c
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ramstage-y += board_id.c
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subdirs-y += variants/baseboard
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CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include
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51
src/mainboard/intel/icelake_rvp/board_id.c
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51
src/mainboard/intel/icelake_rvp/board_id.c
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@ -0,0 +1,51 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2018 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include "board_id.h"
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#include <boardid.h>
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#include <ec/acpi/ec.h>
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#include <stdint.h>
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#include <ec/google/chromeec/ec.h>
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static int get_board_id_via_ext_ec(void)
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{
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uint32_t id = BOARD_ID_INIT;
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if (google_chromeec_get_board_version(&id))
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id = BOARD_ID_UNKNOWN;
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return id;
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}
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/* Get Board ID via EC I/O port write/read */
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int get_board_id(void)
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{
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MAYBE_STATIC int id = -1;
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if (id < 0) {
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if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
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id = get_board_id_via_ext_ec();
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else{
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uint8_t buffer[2];
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uint8_t index;
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if (send_ec_command(EC_FAB_ID_CMD) == 0) {
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for (index = 0; index < sizeof(buffer); index++)
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buffer[index] = recv_ec_data();
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id = (buffer[0] << 8) | buffer[1];
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}
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}
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}
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return id;
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}
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28
src/mainboard/intel/icelake_rvp/board_id.h
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28
src/mainboard/intel/icelake_rvp/board_id.h
Normal file
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@ -0,0 +1,28 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2018 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _MAINBOARD_BOARD_ID_H_
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#define _MAINBOARD_BOARD_ID_H_
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/* Board/FAB ID Command */
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#define EC_FAB_ID_CMD 0x0D
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/*
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* Returns board information (board id[15:8] and
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* Fab info[7:0]) on success and < 0 on error
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*/
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int get_board_id(void);
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#endif /* _MAINBOARD_BOARD_ID_H_ */
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@ -17,11 +17,11 @@ romstage-y += spd_util.c
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SPD_BIN = $(obj)/spd.bin
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SPD_SOURCES = empty # 0b000
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SPD_SOURCES += empty # 0b001
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SPD_SOURCES += empty # 0b001
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SPD_SOURCES += empty # 0b011
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SPD_SOURCES += empty # 0b100
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SPD_SOURCES += empty # 0b101
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SPD_SOURCES += empty # 0b110
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SPD_SOURCES += empty # 0b111
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SPD_SOURCES = empty # 0b000
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SPD_SOURCES += samsung_K4F6E304HBMGCJ # 1b001
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SPD_SOURCES += empty # 2b010
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SPD_SOURCES += empty # 3b011
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SPD_SOURCES += samsung_K4F6E304HBMGCJ # 4b100
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SPD_SOURCES += empty # 5b101
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SPD_SOURCES += samsung_K4F6E304HBMGCJ # 6b110
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SPD_SOURCES += empty # 7b111
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@ -0,0 +1,32 @@
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23 11 10 0E 15 19 94 08 00 40 00 00 0A 22 00 00
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00 00 05 0F 92 54 01 00 8A 00 90 A8 90 A0 05 D0
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02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 92 00 A7 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 20 00 00 00 20 20 20 20 20 20 20
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20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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@ -13,11 +13,21 @@
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* GNU General Public License for more details.
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*/
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#include <arch/byteorder.h>
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#include <arch/cpu.h>
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#include <console/console.h>
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#include <intelblocks/mp_init.h>
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#include <stdint.h>
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#include <string.h>
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#include "../board_id.h"
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#include "spd.h"
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enum icl_dimm_type {
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icl_u_ddr4 = 0,
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icl_u_lpddr4 = 1,
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icl_u_lpddr4_type_3 = 4,
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icl_y_lpddr4 = 6
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};
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void mainboard_fill_dq_map_ch0(void *dq_map_ptr)
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{
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/* DQ byte map Ch0 */
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@ -37,30 +47,61 @@ void mainboard_fill_dq_map_ch1(void *dq_map_ptr)
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memcpy(dq_map_ptr, dq_map, sizeof(dq_map));
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}
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static uint8_t get_spd_index(void)
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{
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uint8_t spd_index = (get_board_id() & 0x1F) & 0x7;
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return spd_index;
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}
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void mainboard_fill_dqs_map_ch0(void *dqs_map_ptr)
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{
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/* DQS CPU<>DRAM map Ch0 */
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const u8 dqs_map_u[8] = { 0, 3, 2, 1, 5, 6, 7, 4 };
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const u8 dqs_map_u_ddr[8] = { 2, 0, 1, 3, 6, 4, 7, 5 };
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const u8 dqs_map_u_lpddr[8] = { 2, 3, 0, 1, 7, 6, 4, 5 };
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const u8 dqs_map_u_lpddr_type_3[8] = { 2, 3, 1, 0, 7, 6, 4, 5 };
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const u8 dqs_map_y_lpddr[8] = { 0, 1, 2, 3, 4, 5, 6, 7 };
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const u8 dqs_map_y[8] = { 2, 0, 3, 1, 6, 5, 7, 4 };
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if (IS_ENABLED(CONFIG_BOARD_INTEL_ICELAKE_RVPU))
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memcpy(dqs_map_ptr, dqs_map_u, sizeof(dqs_map_u));
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else
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memcpy(dqs_map_ptr, dqs_map_y, sizeof(dqs_map_y));
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switch (get_spd_index()) {
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case icl_u_ddr4:
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memcpy(dqs_map_ptr, dqs_map_u_ddr, sizeof(dqs_map_u_ddr));
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break;
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case icl_u_lpddr4:
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memcpy(dqs_map_ptr, dqs_map_u_lpddr, sizeof(dqs_map_u_lpddr));
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break;
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case icl_u_lpddr4_type_3:
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memcpy(dqs_map_ptr, dqs_map_u_lpddr_type_3,
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sizeof(dqs_map_u_lpddr_type_3));
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break;
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case icl_y_lpddr4:
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memcpy(dqs_map_ptr, dqs_map_y_lpddr, sizeof(dqs_map_y_lpddr));
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break;
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default:
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break;
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}
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}
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void mainboard_fill_dqs_map_ch1(void *dqs_map_ptr)
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{
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/* DQS CPU<>DRAM map Ch1 */
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const u8 dqs_map_u[8] = { 3, 0, 1, 2, 5, 6, 4, 7 };
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const u8 dqs_map_u_ddr[8] = { 1, 3, 2, 0, 5, 7, 6, 4 };
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const u8 dqs_map_u_lpddr[8] = { 1, 0, 3, 2, 5, 4, 7, 6 };
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const u8 dqs_map_y_lpddr[8] = { 0, 1, 2, 3, 5, 4, 7, 6 };
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const u8 dqs_map_y[8] = { 3, 1, 2, 0, 4, 5, 6, 7 };
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if (IS_ENABLED(CONFIG_BOARD_INTEL_ICELAKE_RVPU))
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memcpy(dqs_map_ptr, dqs_map_u, sizeof(dqs_map_u));
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else
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memcpy(dqs_map_ptr, dqs_map_y, sizeof(dqs_map_y));
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switch (get_spd_index()) {
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case icl_u_ddr4:
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memcpy(dqs_map_ptr, dqs_map_u_ddr, sizeof(dqs_map_u_ddr));
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break;
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case icl_u_lpddr4:
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case icl_u_lpddr4_type_3:
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memcpy(dqs_map_ptr, dqs_map_u_lpddr, sizeof(dqs_map_u_lpddr));
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break;
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case icl_y_lpddr4:
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memcpy(dqs_map_ptr, dqs_map_y_lpddr, sizeof(dqs_map_y_lpddr));
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break;
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default:
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break;
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}
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}
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void mainboard_fill_rcomp_res_data(void *rcomp_ptr)
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@ -70,11 +111,45 @@ void mainboard_fill_rcomp_res_data(void *rcomp_ptr)
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memcpy(rcomp_ptr, RcompResistor, sizeof(RcompResistor));
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}
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/*
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* get processor id using cpuid eax=1
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* return value will be in EAX register
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*/
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static uint32_t get_cpuid(void)
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{
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struct cpuid_result cpuidr;
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cpuidr = cpuid(1);
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return cpuidr.eax;
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}
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void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr)
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{
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/* Rcomp target */
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static const u16 RcompTarget[RCOMP_TARGET_PARAMS] = {
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static const u16 RcompTarget_DDR4[RCOMP_TARGET_PARAMS] = {
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100, 33, 32, 33, 28 };
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static const u16 RcompTarget_LPDDR4_Ax[RCOMP_TARGET_PARAMS] = {
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80, 40, 40, 40, 30 };
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static const u16 RcompTarget_LPDDR4_Bx[RCOMP_TARGET_PARAMS] = {
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60, 20, 20, 20, 20 };
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memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget));
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switch (get_spd_index()) {
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case icl_u_ddr4:
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memcpy(rcomp_strength_ptr, RcompTarget_DDR4,
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sizeof(RcompTarget_DDR4));
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break;
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case icl_y_lpddr4:
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case icl_u_lpddr4:
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case icl_u_lpddr4_type_3:
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if (get_cpuid() == CPUID_ICELAKE_A0)
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memcpy(rcomp_strength_ptr, RcompTarget_LPDDR4_Ax,
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sizeof(RcompTarget_LPDDR4_Ax));
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else
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memcpy(rcomp_strength_ptr, RcompTarget_LPDDR4_Bx,
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sizeof(RcompTarget_LPDDR4_Bx));
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break;
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default:
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break;
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}
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}
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