src/mb/google/hatch: remove "sushi" variant.
Sushi is not a real product, just a test of the new_variant program. The effort to keep it up-to-date with the rest of Hatch is no longer worth it. Remove the variant. BUG=b:168030592 TEST=build bot is successful, hatch-cq builds successfully Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org> Change-Id: I2b0036f3cbdea4bfaed1274ab87a20d24c75de57 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45175 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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@ -140,7 +140,6 @@ config MAINBOARD_PART_NUMBER
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default "Nightfury" if BOARD_GOOGLE_NIGHTFURY
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default "Puff" if BOARD_GOOGLE_PUFF
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default "Stryke" if BOARD_GOOGLE_STRYKE
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default "Sushi" if BOARD_GOOGLE_SUSHI
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default "Wyvern" if BOARD_GOOGLE_WYVERN
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default "Dooly" if BOARD_GOOGLE_DOOLY
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@ -174,7 +173,6 @@ config VARIANT_DIR
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default "nightfury" if BOARD_GOOGLE_NIGHTFURY
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default "puff" if BOARD_GOOGLE_PUFF
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default "stryke" if BOARD_GOOGLE_STRYKE
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default "sushi" if BOARD_GOOGLE_SUSHI
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default "wyvern" if BOARD_GOOGLE_WYVERN
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default "dooly" if BOARD_GOOGLE_DOOLY
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@ -90,10 +90,6 @@ config BOARD_GOOGLE_STRYKE
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bool "-> Stryke"
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select BOARD_GOOGLE_BASEBOARD_HATCH
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config BOARD_GOOGLE_SUSHI
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bool "-> Sushi"
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select BOARD_GOOGLE_BASEBOARD_HATCH
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config BOARD_GOOGLE_WYVERN
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bool "-> Wyvern"
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select BOARD_GOOGLE_BASEBOARD_PUFF
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@ -1,3 +0,0 @@
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## SPDX-License-Identifier: GPL-2.0-only
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SPD_SOURCES =
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@ -1,3 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <baseboard/acpi/dptf.asl>
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@ -1,8 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef VARIANT_EC_H
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#define VARIANT_EC_H
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#include <baseboard/ec.h>
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#endif
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@ -1,15 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef VARIANT_GPIO_H
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#define VARIANT_GPIO_H
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#include <baseboard/gpio.h>
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/* Memory configuration board straps */
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/* Copied from baseboard and may need to change for the new variant. */
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#define GPIO_MEM_CONFIG_0 GPP_F20
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#define GPIO_MEM_CONFIG_1 GPP_F21
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#define GPIO_MEM_CONFIG_2 GPP_F11
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#define GPIO_MEM_CONFIG_3 GPP_F22
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#endif
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@ -1,6 +0,0 @@
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chip soc/intel/cannonlake
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device domain 0 on
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end
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end
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