From 4057ab4f314ae17402fa7635d17d86304b9ce060 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Fri, 24 Mar 2023 19:26:49 +0100 Subject: [PATCH] soc/amd/common/block/cpu/tsc/tsc_freq: use get_pstate_core_freq Use get_pstate_core_freq instead of open-coding the calculations in tsc_freq_mhz. In the case of the CPU frequency divider being 0, get_pstate_core_freq will return 0; in this case that shouldn't happen, TSC_DEFAULT_FREQ_MHZ will be used as frequency, since for the TSC frequency it's better to err on the end of the expected frequency being too high which will cause longer than expected delays instead of too short delays. Now that the code is using get_pstate_core_freq, this code is valid for Glinda too, so also remove the comment on the SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H option being selected in the Glinda Kconfig. This Kconfig option will be renamed in a follow-up patch. Signed-off-by: Felix Held Change-Id: I01168834d4018c92f44782eda0c65b1aa392030d Reviewed-on: https://review.coreboot.org/c/coreboot/+/74013 Tested-by: build bot (Jenkins) Reviewed-by: Eric Lai Reviewed-by: Martin Roth --- src/soc/amd/common/block/cpu/tsc/tsc_freq.c | 21 +++++++-------------- src/soc/amd/glinda/Kconfig | 2 +- 2 files changed, 8 insertions(+), 15 deletions(-) diff --git a/src/soc/amd/common/block/cpu/tsc/tsc_freq.c b/src/soc/amd/common/block/cpu/tsc/tsc_freq.c index fbbf399731..f177b77673 100644 --- a/src/soc/amd/common/block/cpu/tsc/tsc_freq.c +++ b/src/soc/amd/common/block/cpu/tsc/tsc_freq.c @@ -1,9 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +#include #include #include #include #include +#include static unsigned long mhz; @@ -13,31 +15,22 @@ static unsigned long mhz; unsigned long tsc_freq_mhz(void) { - msr_t msr; - uint8_t cpufid; - uint8_t cpudid; + union pstate_msr pstate_reg; uint8_t high_state; if (mhz) return mhz; high_state = rdmsr(PS_LIM_REG).lo & 0x7; - msr = rdmsr(PSTATE_MSR(high_state)); - if (!(msr.hi & 0x80000000)) + pstate_reg.raw = rdmsr(PSTATE_MSR(high_state)).raw; + if (!pstate_reg.pstate_en) die("Unknown error: cannot determine P-state 0\n"); - cpufid = (msr.lo & 0xff); - cpudid = (msr.lo & 0x3f00) >> 8; + mhz = get_pstate_core_freq(pstate_reg); - /* normally core frequency is calculated as (fid * 25) / (did / 8) */ - if (!cpudid) { + if (!mhz) { mhz = TSC_DEFAULT_FREQ_MHZ; printk(BIOS_ERR, "Invalid divisor, set TSC frequency to %ldMHz\n", mhz); - } else if ((cpudid >= 8) && (cpudid <= 0x30)) { - mhz = (200 * cpufid) / cpudid; - } else { - mhz = 25 * cpufid; - printk(BIOS_ERR, "Invalid frequency divisor 0x%x, assume 1\n", cpudid); } return mhz; diff --git a/src/soc/amd/glinda/Kconfig b/src/soc/amd/glinda/Kconfig index c68ee47b00..ac46395480 100644 --- a/src/soc/amd/glinda/Kconfig +++ b/src/soc/amd/glinda/Kconfig @@ -71,7 +71,7 @@ config SOC_AMD_GLINDA select SOC_AMD_COMMON_BLOCK_SMU_SX_ENTRY # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_SPI # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_SVI3 - select SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H # FIXME: This is likely incompatible + select SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H select SOC_AMD_COMMON_BLOCK_UART # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_UCODE # TODO: Check if this is still correct select SOC_AMD_COMMON_FSP_CCX_CPPC_HOB # TODO: Check if this is still correct