soc/intel/fsp_baytrail: Add VBOOT support
* Add vbnv_cmos_failed function to SoC. * Add VBOOT starts in romstage select. Change-Id: I90a051e2b8d303c918bef976d0bb07aae0b1f5b3 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/27728 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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@ -47,6 +47,9 @@ config CPU_SPECIFIC_OPTIONS
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# Microcode header files are delivered in FSP package
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# Microcode header files are delivered in FSP package
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select USES_MICROCODE_HEADER_FILES if HAVE_FSP_BIN
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select USES_MICROCODE_HEADER_FILES if HAVE_FSP_BIN
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config VBOOT
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select VBOOT_STARTS_IN_ROMSTAGE
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config SOC_INTEL_FSP_BAYTRAIL_MD
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config SOC_INTEL_FSP_BAYTRAIL_MD
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bool
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bool
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default n
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default n
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@ -42,6 +42,7 @@ ramstage-y += northcluster.c
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ramstage-y += ramstage.c
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ramstage-y += ramstage.c
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ramstage-y += gpio.c
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ramstage-y += gpio.c
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romstage-y += gpio.c
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romstage-y += gpio.c
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romstage-y += pmutil.c
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ramstage-y += pmutil.c
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ramstage-y += pmutil.c
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ramstage-y += southcluster.c
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ramstage-y += southcluster.c
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romstage-y += reset.c
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romstage-y += reset.c
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@ -15,14 +15,16 @@
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#include <stdint.h>
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#include <stdint.h>
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#include <arch/io.h>
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#include <arch/io.h>
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#include <cbmem.h>
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#include <console/console.h>
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#include <console/console.h>
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#include <soc/iomap.h>
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#include <soc/iomap.h>
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#include <soc/lpc.h>
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#include <soc/lpc.h>
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#include <soc/pci_devs.h>
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#include <soc/pci_devs.h>
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#include <soc/pmc.h>
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#include <soc/pmc.h>
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#include <security/vboot/vbnv.h>
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#if defined(__SMM__)
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#if defined(__SIMPLE_DEVICE__)
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static const pci_devfn_t pcu_dev = PCI_DEV(0, PCU_DEV, 0);
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static const pci_devfn_t pcu_dev = PCI_DEV(0, PCU_DEV, 0);
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@ -31,7 +33,7 @@ static inline pci_devfn_t get_pcu_dev(void)
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return pcu_dev;
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return pcu_dev;
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}
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}
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#else /* !__SMM__ */
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#else /* !__SIMPLE_DEVICE__ */
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#include <device/device.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci.h>
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@ -358,3 +360,22 @@ void clear_pmc_status(void)
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write32((u32 *)(PMC_BASE_ADDRESS + GEN_PMCON1), gen_pmcon1 & ~RPS);
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write32((u32 *)(PMC_BASE_ADDRESS + GEN_PMCON1), gen_pmcon1 & ~RPS);
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write32((u32 *)(PMC_BASE_ADDRESS + PRSTS), prsts);
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write32((u32 *)(PMC_BASE_ADDRESS + PRSTS), prsts);
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}
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}
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int vbnv_cmos_failed(void)
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{
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uint32_t gen_pmcon1;
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int rtc_fail;
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struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE);
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if (ps != NULL)
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gen_pmcon1 = ps->gen_pmcon1;
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else
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gen_pmcon1 = read32((u32 *)(PMC_BASE_ADDRESS + GEN_PMCON1));
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rtc_fail = !!(gen_pmcon1 & RPS);
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if (rtc_fail)
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printk(BIOS_DEBUG, "RTC failure.\n");
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return rtc_fail;
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}
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