GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

mb/google/rex: Correct EC-is-trusted logic 

Fix EC_IN_RW config for Rex. Dauntless on Rex does not have an EC_IN_RW GPIO pin.

Port of commit 7f339c6050 ("mb/google/corsola: Correct EC-is-trusted logic")

BUG=b:243950850
TEST=Built and booted to Google Rex.

Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I97e5c752b4f36c9221137903f755837880f6b1c4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67208
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
This commit is contained in:
Kapil Porwal 2022-08-30 11:54:45 +00:00 committed by Subrata Banik
parent 5072ed2bb2
commit 4060860942
2 changed files with 3 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
src/mainboard/google/rex/chromeos.c
View File

@ -12,7 +12,7 @@ void fill_lb_gpios(struct lb_gpios *gpios)
{-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, get_lid_switch(), "lid"},
{-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, 0, "power"},
{-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
{GPIO_EC_IN_RW, ACTIVE_HIGH, gpio_get(GPIO_EC_IN_RW), "EC in RW"}, {-1, ACTIVE_HIGH, 0, "EC in RW"},
}; };
lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
} }
@ -24,6 +24,6 @@ int get_write_protect_state(void)
int get_ec_is_trusted(void) int get_ec_is_trusted(void)
{ {
/* EC is trusted if not in RW. */ /* VB2_CONTEXT_EC_TRUSTED should be set according to the Ti50 boot mode. */
return !gpio_get(GPIO_EC_IN_RW); return 0;
} }

2
src/mainboard/google/rex/variants/baseboard/rex/include/baseboard/gpio.h
View File

@ -9,8 +9,6 @@
/* Fixme: Update proper GPIO number based on schematics */ /* Fixme: Update proper GPIO number based on schematics */
/* WP signal to PCH */ /* WP signal to PCH */
#define GPIO_PCH_WP GPP_H10 #define GPIO_PCH_WP GPP_H10
/* EC in RW or RO */
#define GPIO_EC_IN_RW 0
/* GPIO IRQ for tight timestamps / wake support */ /* GPIO IRQ for tight timestamps / wake support */
#define EC_SYNC_IRQ GPP_A17_IRQ #define EC_SYNC_IRQ GPP_A17_IRQ
/* eSPI virtual wire reporting */ /* eSPI virtual wire reporting */