diff --git a/src/mainboard/amd/birman/board_phoenix.fmd b/src/mainboard/amd/birman/board_phoenix.fmd index 32c7a5a6dd..6f7af56ecb 100644 --- a/src/mainboard/amd/birman/board_phoenix.fmd +++ b/src/mainboard/amd/birman/board_phoenix.fmd @@ -3,6 +3,6 @@ FLASH@0xFF000000 16M { EC 4K FMAP 4K COREBOOT(CBFS) - RW_MRC_CACHE 120K + RW_MRC_CACHE 256K } } diff --git a/src/mainboard/amd/birman/chromeos_phoenix.fmd b/src/mainboard/amd/birman/chromeos_phoenix.fmd index 538dfbd1c6..dca61fc552 100644 --- a/src/mainboard/amd/birman/chromeos_phoenix.fmd +++ b/src/mainboard/amd/birman/chromeos_phoenix.fmd @@ -29,6 +29,6 @@ FLASH@0xFF000000 16M { RW_NVRAM(PRESERVE) 20K SMMSTORE(PRESERVE) 64K RW_LEGACY(CBFS) - RW_MRC_CACHE(PRESERVE) 120K + RW_MRC_CACHE(PRESERVE) 256K } } diff --git a/src/mainboard/amd/mayan/board.fmd b/src/mainboard/amd/mayan/board.fmd index 32c7a5a6dd..6f7af56ecb 100644 --- a/src/mainboard/amd/mayan/board.fmd +++ b/src/mainboard/amd/mayan/board.fmd @@ -3,6 +3,6 @@ FLASH@0xFF000000 16M { EC 4K FMAP 4K COREBOOT(CBFS) - RW_MRC_CACHE 120K + RW_MRC_CACHE 256K } } diff --git a/src/mainboard/amd/mayan/chromeos.fmd b/src/mainboard/amd/mayan/chromeos.fmd index 538dfbd1c6..dca61fc552 100644 --- a/src/mainboard/amd/mayan/chromeos.fmd +++ b/src/mainboard/amd/mayan/chromeos.fmd @@ -29,6 +29,6 @@ FLASH@0xFF000000 16M { RW_NVRAM(PRESERVE) 20K SMMSTORE(PRESERVE) 64K RW_LEGACY(CBFS) - RW_MRC_CACHE(PRESERVE) 120K + RW_MRC_CACHE(PRESERVE) 256K } } diff --git a/src/soc/amd/phoenix/Kconfig b/src/soc/amd/phoenix/Kconfig index 03cf8366ff..b108c8f2da 100644 --- a/src/soc/amd/phoenix/Kconfig +++ b/src/soc/amd/phoenix/Kconfig @@ -116,11 +116,11 @@ config PSP_APOB_DRAM_ADDRESS config PSP_APOB_DRAM_SIZE hex - default 0x1E000 + default 0x40000 config PSP_SHAREDMEM_BASE hex - default 0x201F000 if VBOOT + default 0x2041000 if VBOOT default 0x0 help This variable defines the base address in DRAM memory where PSP copies @@ -165,7 +165,7 @@ config C_ENV_BOOTBLOCK_SIZE config ROMSTAGE_ADDR hex - default 0x2040000 + default 0x2060000 help Sets the address in DRAM where romstage should be loaded. @@ -177,7 +177,7 @@ config ROMSTAGE_SIZE config FSP_M_ADDR hex - default 0x20C0000 + default 0x20E0000 help Sets the address in DRAM where FSP-M should be loaded. cbfstool performs relocation of FSP-M to this address. @@ -197,7 +197,7 @@ config FSP_TEMP_RAM_SIZE config VERSTAGE_ADDR hex depends on VBOOT_SEPARATE_VERSTAGE - default 0x2180000 + default 0x21A0000 help Sets the address in DRAM where verstage should be loaded if running as a separate stage on x86.