mb/ocp/deltalake: Populate SMBIOS data and set the read PPIN to BMC
1. Populate SMBIOS data from OCP_DMI driver read from FRU and PPIN MSR for OEM string 1 to 6, add string 8 for PCIE configuration. 2. Set the read PPIN MSR to BMC. Tested on OCP Delta Lake. Change-Id: I9127cf5da1c56d8012694d070615aec24cc22fdf Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41279 Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -9,6 +9,7 @@ config BOARD_SPECIFIC_OPTIONS
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select SOC_INTEL_COOPERLAKE_SP
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select SUPERIO_ASPEED_AST2400
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select IPMI_KCS
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select OCP_DMI
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config IPMI_KCS_REGISTER_SPACING
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int
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@ -4,7 +4,7 @@ bootblock-y += bootblock.c
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romstage-y += romstage.c
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ramstage-y += ramstage.c
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ramstage-y += ramstage.c ipmi.c
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ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c
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CPPFLAGS_common += -Isrc/mainboard/$(MAINBOARDDIR)/
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@ -0,0 +1,48 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <console/console.h>
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#include <drivers/ipmi/ipmi_kcs.h>
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#include <drivers/ipmi/ipmi_ops.h>
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#include "ipmi.h"
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enum cb_err ipmi_set_ppin(struct ppin_req *req)
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{
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int ret;
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struct ipmi_rsp rsp;
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ret = ipmi_kcs_message(CONFIG_BMC_KCS_BASE, IPMI_NETFN_OEM, 0x0, IPMI_OEM_SET_PPIN,
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(const unsigned char *) req, sizeof(*req),
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(unsigned char *) &rsp, sizeof(rsp));
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if (ret < sizeof(struct ipmi_rsp) || rsp.completion_code) {
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printk(BIOS_ERR, "IPMI: %s command failed (ret=%d resp=0x%x)\n",
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__func__, ret, rsp.completion_code);
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return CB_ERR;
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}
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return CB_SUCCESS;
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}
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enum cb_err ipmi_get_pcie_config(uint8_t *pcie_config)
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{
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int ret;
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struct ipmi_config_rsp {
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struct ipmi_rsp resp;
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uint8_t config;
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} __packed;
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struct ipmi_config_rsp rsp;
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ret = ipmi_kcs_message(CONFIG_BMC_KCS_BASE, IPMI_NETFN_OEM, 0x0,
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IPMI_OEM_GET_PCIE_CONFIG, NULL, 0, (unsigned char *) &rsp,
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sizeof(rsp));
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if (ret < sizeof(struct ipmi_rsp) || rsp.resp.completion_code) {
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printk(BIOS_ERR, "IPMI: %s command failed (ret=%d resp=0x%x)\n",
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__func__, ret, rsp.resp.completion_code);
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return CB_ERR;
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}
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*pcie_config = rsp.config;
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return CB_SUCCESS;
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}
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@ -0,0 +1,27 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#ifndef DELTALAKE_IPMI_H
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#define DELTALAKE_IPMI_H
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#include <stdint.h>
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#define IPMI_NETFN_OEM 0x30
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#define IPMI_OEM_SET_PPIN 0x77
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#define IPMI_OEM_GET_PCIE_CONFIG 0xf4
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#define PCIE_CONFIG_UNKNOWN 0x0
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#define PCIE_CONFIG_A 0x1
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#define PCIE_CONFIG_B 0x2
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#define PCIE_CONFIG_C 0x3
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#define PCIE_CONFIG_D 0x4
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struct ppin_req {
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uint32_t cpu0_lo;
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uint32_t cpu0_hi;
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uint32_t cpu1_lo;
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uint32_t cpu1_hi;
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} __packed;
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enum cb_err ipmi_set_ppin(struct ppin_req *req);
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enum cb_err ipmi_get_pcie_config(uint8_t *config);
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#endif
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@ -1,7 +1,72 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <console/console.h>
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#include <drivers/ipmi/ipmi_ops.h>
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#include <drivers/ocp/dmi/ocp_dmi.h>
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#include <soc/ramstage.h>
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#include "ipmi.h"
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extern struct fru_info_str fru_strings;
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static void dl_oem_smbios_strings(struct device *dev, struct smbios_type11 *t)
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{
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uint8_t pcie_config = 0;
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/* OEM string 1 to 6 */
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ocp_oem_smbios_strings(dev, t);
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/* TODO: Add real OEM string 7, add TBF for now */
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t->count = smbios_add_oem_string(t->eos, TBF);
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/* Add OEM string 8 */
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if (ipmi_get_pcie_config(&pcie_config) == CB_SUCCESS) {
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switch (pcie_config) {
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case PCIE_CONFIG_UNKNOWN:
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t->count = smbios_add_oem_string(t->eos, "0x0: Unknown");
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break;
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case PCIE_CONFIG_A:
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t->count = smbios_add_oem_string(t->eos, "0x1: YV3 Config-A");
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break;
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case PCIE_CONFIG_B:
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t->count = smbios_add_oem_string(t->eos, "0x2: YV3 Config-B");
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break;
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case PCIE_CONFIG_C:
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t->count = smbios_add_oem_string(t->eos, "0x3: YV3 Config-C");
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break;
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case PCIE_CONFIG_D:
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t->count = smbios_add_oem_string(t->eos, "0x4: YV3 Config-D");
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break;
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default:
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t->count = smbios_add_oem_string(t->eos, "Check BMC return data");
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}
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} else {
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printk(BIOS_ERR, "Failed to get IPMI PCIe config\n");
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}
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}
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static void mainboard_enable(struct device *dev)
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{
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dev->ops->get_smbios_strings = dl_oem_smbios_strings,
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read_fru_areas(CONFIG_BMC_KCS_BASE, CONFIG_FRU_DEVICE_ID, 0, &fru_strings);
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}
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void mainboard_silicon_init_params(FSPS_UPD *params)
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{
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}
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static void mainboard_final(void *chip_info)
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{
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struct ppin_req req = {0};
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req.cpu0_lo = xeon_sp_ppin[0].lo;
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req.cpu0_hi = xeon_sp_ppin[0].hi;
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/* Set PPIN to BMC */
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if (ipmi_set_ppin(&req) != CB_SUCCESS)
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printk(BIOS_ERR, "ipmi_set_ppin failed\n");
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}
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struct chip_operations mainboard_ops = {
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.enable_dev = mainboard_enable,
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.final = mainboard_final,
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};
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