mb/amd: Add Pollock CRB Cereme as Mandolin variant
Even though the devicetrees of Mandolin and Cereme are relatively similar, they are kept as separate files instead of using devicetree overrides to facilitate creating mainboard ports based on those CRBs. The two boards are reference boards for different zen/zen+ APU platforms that share the silicon, but use different packages. This is also consistent with the google/zork boards that have two different full base devicetrees for the two different platforms and then use devicetree overrides for the different variants of the two reference designs. BUG=b:159617786,b:169644059 BRANCH=zork Change-Id: Ief8a05b0a360563d26a81941720b78014feb0d25 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42786 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Felix Held
Felix Held
parent
4ae3e41deb
commit
407b866a3e
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@ -1,6 +1,6 @@
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# SPDX-License-Identifier: GPL-2.0-only
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if BOARD_AMD_MANDOLIN
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if BOARD_AMD_MANDOLIN || BOARD_AMD_CEREME
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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@ -8,6 +8,7 @@ config BOARD_SPECIFIC_OPTIONS
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select SOC_AMD_PICASSO
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select HAVE_ACPI_TABLES
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select BOARD_ROMSIZE_KB_8192 if BOARD_AMD_MANDOLIN
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select BOARD_ROMSIZE_KB_16384 if BOARD_AMD_CEREME
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select AZALIA_PLUGIN_SUPPORT
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select HAVE_ACPI_RESUME
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select DRIVERS_UART_ACPI
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@ -31,6 +32,7 @@ config AMD_LPC_DEBUG_CARD
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config CBFS_SIZE
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hex
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default 0x7cf000 if BOARD_AMD_MANDOLIN # Maximum size for the Mandolin FMAP
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default 0xfcf000 if BOARD_AMD_CEREME # Maximum size for the Cereme FMAP
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config MAINBOARD_DIR
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string
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@ -39,10 +41,12 @@ config MAINBOARD_DIR
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config VARIANT_DIR
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string
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default "mandolin" if BOARD_AMD_MANDOLIN
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default "cereme" if BOARD_AMD_CEREME
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config MAINBOARD_PART_NUMBER
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string
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default "MANDOLIN" if BOARD_AMD_MANDOLIN
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default "CEREME" if BOARD_AMD_CEREME
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config DEVICETREE
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string
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@ -59,6 +63,7 @@ config ONBOARD_VGA_IS_PRIMARY
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config AMD_FWM_POSITION_INDEX
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int
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default 3 if BOARD_AMD_MANDOLIN
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default 4 if BOARD_AMD_CEREME
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help
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TODO: might need to be adapted for better placement of files in cbfs
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@ -70,6 +75,7 @@ config MANDOLIN_MCHP_FW_FILE
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string
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depends on MANDOLIN_HAVE_MCHP_FW
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default "3rdparty/blobs/mainboard/amd/mandolin/EC_mandolin.bin" if BOARD_AMD_MANDOLIN
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default "3rdparty/blobs/mainboard/amd/mandolin/EC_cereme.bin" if BOARD_AMD_CEREME
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if !AMD_LPC_DEBUG_CARD
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choice
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@ -106,19 +112,22 @@ config VGA_BIOS_DGPU_ID
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config VGA_BIOS_DGPU_FILE
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string
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default "3rdparty/amd_blobs/picasso/PicassoGenericVbios.bin" if BOARD_AMD_MANDOLIN
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default "3rdparty/amd_blobs/picasso/Raven2GenericVbios.bin" if BOARD_AMD_CEREME
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config EFS_SPI_READ_MODE
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int
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default 0 if EM100
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default 0 if BOARD_AMD_CEREME
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default 3
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config EFS_SPI_SPEED
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int
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default 3 if EM100
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default 1 if BOARD_AMD_CEREME
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default 0
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config EFS_SPI_MICRON_FLAG
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int
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default 0
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endif # BOARD_AMD_MANDOLIN
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endif # BOARD_AMD_MANDOLIN || BOARD_AMD_CEREME
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@ -1,2 +1,5 @@
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config BOARD_AMD_MANDOLIN
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bool "Mandolin"
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config BOARD_AMD_CEREME
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bool "Cereme"
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@ -10,7 +10,11 @@ ifneq ($(CONFIG_PICASSO_LPC_IOMUX),y)
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ramstage-y += emmc_gpio.c
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endif
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ifeq ($(CONFIG_BOARD_AMD_MANDOLIN),y)
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APCB_SOURCES = $(MAINBOARD_BLOBS_DIR)/APCB_mandolin.bin
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else # CONFIG_BOARD_AMD_CEREME
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APCB_SOURCES = $(MAINBOARD_BLOBS_DIR)/APCB_cereme.bin
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endif
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PHONY+=add_mchp_fw
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INTERMEDIATE+=add_mchp_fw
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@ -0,0 +1,8 @@
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FLASH@0xFF000000 16M {
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BIOS {
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EC 0x20000
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RW_MRC_CACHE 0x10000
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FMAP 0x1000
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COREBOOT(CBFS)
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}
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}
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@ -0,0 +1,184 @@
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# SPDX-License-Identifier: GPL-2.0-only
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chip soc/amd/picasso
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register "acp_pin_cfg" = "I2S_PINS_MAX_HDA"
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# Set FADT Configuration
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register "fadt_boot_arch" = "ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042"
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register "fadt_flags" = "ACPI_FADT_SLEEP_BUTTON" # See table 5-34 ACPI 6.3 spec
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register "emmc_config" = "{
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.timing = SD_EMMC_DISABLE,
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}"
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register "has_usb2_phy_tune_params" = "1"
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# Controller0 Port0 Default
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register "usb_2_port_tune_params[0]" = "{
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.com_pds_tune = 0x03,
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.sq_rx_tune = 0x3,
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.tx_fsls_tune = 0x3,
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.tx_pre_emp_amp_tune = 0x03,
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.tx_pre_emp_pulse_tune = 0x0,
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.tx_rise_tune = 0x1,
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.rx_vref_tune = 0x6,
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.tx_hsxv_tune = 0x3,
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.tx_res_tune = 0x01,
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}"
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# Controller0 Port1 Default
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register "usb_2_port_tune_params[1]" = "{
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.com_pds_tune = 0x03,
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.sq_rx_tune = 0x3,
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.tx_fsls_tune = 0x3,
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.tx_pre_emp_amp_tune = 0x03,
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.tx_pre_emp_pulse_tune = 0x0,
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.tx_rise_tune = 0x1,
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.rx_vref_tune = 0x6,
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.tx_hsxv_tune = 0x3,
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.tx_res_tune = 0x01,
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}"
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# Controller0 Port2 Default
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register "usb_2_port_tune_params[2]" = "{
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.com_pds_tune = 0x03,
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.sq_rx_tune = 0x3,
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.tx_fsls_tune = 0x3,
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.tx_pre_emp_amp_tune = 0x03,
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.tx_pre_emp_pulse_tune = 0x0,
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.tx_rise_tune = 0x1,
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.rx_vref_tune = 0x6,
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.tx_hsxv_tune = 0x3,
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.tx_res_tune = 0x01,
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}"
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# Controller0 Port3 Default
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register "usb_2_port_tune_params[3]" = "{
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.com_pds_tune = 0x03,
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.sq_rx_tune = 0x3,
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.tx_fsls_tune = 0x3,
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.tx_pre_emp_amp_tune = 0x03,
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.tx_pre_emp_pulse_tune = 0x0,
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.tx_rise_tune = 0x1,
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.rx_vref_tune = 0x6,
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.tx_hsxv_tune = 0x3,
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.tx_res_tune = 0x01,
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}"
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# Controller0 Port4 Default
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register "usb_2_port_tune_params[4]" = "{
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.com_pds_tune = 0x03,
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.sq_rx_tune = 0x3,
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.tx_fsls_tune = 0x3,
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.tx_pre_emp_amp_tune = 0x02,
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.tx_pre_emp_pulse_tune = 0x0,
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.tx_rise_tune = 0x1,
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.rx_vref_tune = 0x5,
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.tx_hsxv_tune = 0x3,
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.tx_res_tune = 0x01,
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}"
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# Controller0 Port5 Default
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register "usb_2_port_tune_params[5]" = "{
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.com_pds_tune = 0x03,
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.sq_rx_tune = 0x3,
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.tx_fsls_tune = 0x3,
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.tx_pre_emp_amp_tune = 0x02,
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.tx_pre_emp_pulse_tune = 0x0,
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.tx_rise_tune = 0x1,
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.rx_vref_tune = 0x5,
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.tx_hsxv_tune = 0x3,
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.tx_res_tune = 0x01,
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}"
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# USB OC pin mapping; all ports share one OC pin
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register "usb_port_overcurrent_pin[0]" = "USB_OC_PIN_0"
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register "usb_port_overcurrent_pin[1]" = "USB_OC_PIN_0"
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register "usb_port_overcurrent_pin[2]" = "USB_OC_PIN_0"
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register "usb_port_overcurrent_pin[3]" = "USB_OC_PIN_0"
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register "usb_port_overcurrent_pin[4]" = "USB_OC_PIN_0"
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register "usb_port_overcurrent_pin[5]" = "USB_OC_PIN_0"
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# SPI Configuration
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register "common_config.spi_config" = "{
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.normal_speed = SPI_SPEED_33M, /* MHz */
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.fast_speed = SPI_SPEED_66M, /* MHz */
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.altio_speed = SPI_SPEED_33M, /* MHz */
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.tpm_speed = SPI_SPEED_33M, /* MHz */
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.read_mode = SPI_READ_MODE_QUAD114,
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}"
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# eSPI Configuration
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register "common_config.espi_config" = "{
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.std_io_decode_bitmap = ESPI_DECODE_IO_0X60_0X64_EN,
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.generic_io_range[0] = {
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.base = 0x662,
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.size = 8,
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},
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.io_mode = ESPI_IO_MODE_SINGLE,
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.op_freq_mhz = ESPI_OP_FREQ_33_MHZ,
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.crc_check_enable = 1,
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.dedicated_alert_pin = 1,
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.periph_ch_en = 0,
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.vw_ch_en = 0,
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.oob_ch_en = 0,
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.flash_ch_en = 0,
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}"
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# genral purpose PCIe clock output configuration
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register "gpp_clk_config[0]" = "GPP_CLK_REQ"
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register "gpp_clk_config[1]" = "GPP_CLK_REQ"
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register "gpp_clk_config[2]" = "GPP_CLK_REQ"
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register "gpp_clk_config[3]" = "GPP_CLK_OFF"
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register "gpp_clk_config[4]" = "GPP_CLK_REQ"
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register "gpp_clk_config[5]" = "GPP_CLK_OFF"
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register "gpp_clk_config[6]" = "GPP_CLK_OFF"
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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device domain 0 on
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subsystemid 0x1022 0x1510 inherit
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device pci 0.0 on end # Root Complex
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device pci 0.2 on end # IOMMU
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device pci 1.0 on end # Dummy Host Bridge
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device pci 1.1 on end # Bridge to PCIe Ethernet chip
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device pci 8.0 on end # Dummy Host Bridge
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device pci 8.1 on # Bridge to Bus A
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device pci 0.0 on end # Internal GPU
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device pci 0.1 on end # Display HDA
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device pci 0.2 on end # Crypto Coprocessor
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device pci 0.3 on end # USB 3.1
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device pci 0.4 off end # USB 3.1
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device pci 0.5 on end # Audio
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device pci 0.6 on end # HDA
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device pci 0.7 on end # non-Sensor Fusion Hub device
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end
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device pci 8.2 on # Bridge to Bus B
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device pci 0.0 off end # AHCI
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device pci 0.1 off end # integrated Ethernet MAC
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device pci 0.2 off end # integrated Ethernet MAC
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end
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device pci 14.0 on end # SMBus
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device pci 14.3 on # D14F3 bridge
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chip superio/smsc/sio1036 # optional debug card
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end
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end
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device pci 14.6 off end # SDHCI
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device pci 18.0 on end # Data fabric [0-7]
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device pci 18.1 on end
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device pci 18.2 on end
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device pci 18.3 on end
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device pci 18.4 on end
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device pci 18.5 on end
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device pci 18.6 on end
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device pci 18.7 on end
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end # domain
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device mmio 0xfedc9000 on end # UART0
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device mmio 0xfedca000 on end # UART1
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device mmio 0xfedce000 off end # UART2
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device mmio 0xfedcf000 off end # UART3
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end # chip soc/amd/picasso
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@ -0,0 +1,32 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <soc/gpio.h>
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#include "../../gpio.h"
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/* GPIO pins used by coreboot should be initialized in bootblock */
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static const struct soc_amd_gpio gpio_set_stage_reset[] = {
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/* not LLB */
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PAD_GPI(GPIO_12, PULL_UP),
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/* not USB_OC1_L */
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PAD_GPI(GPIO_17, PULL_UP),
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/* not USB_OC2_L */
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PAD_GPI(GPIO_18, PULL_UP),
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/* SDIO eMMC power control */
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PAD_NF(GPIO_22, EMMC_PRW_CTRL, PULL_NONE),
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/* PCIe Reset 0 */
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PAD_NF(GPIO_26, PCIE_RST_L, PULL_NONE),
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/* PCIe Reset 1 */
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PAD_NF(GPIO_27, PCIE_RST1_L, PULL_NONE),
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/* eSPI CS# */
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PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE),
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/* FANOUT0 */
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PAD_NF(GPIO_85, FANOUT0, PULL_NONE),
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/* PC beep to codec */
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PAD_NF(GPIO_91, SPKR, PULL_NONE),
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};
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void mainboard_program_early_gpios(void)
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{
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program_gpios(gpio_set_stage_reset, ARRAY_SIZE(gpio_set_stage_reset));
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}
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@ -0,0 +1,33 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <soc/gpio.h>
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#include "../../gpio.h"
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/*
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* As a rule of thumb, GPIO pins used by coreboot should be initialized at
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* bootblock while GPIO pins used only by the OS should be initialized at
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* ramstage.
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*/
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static const struct soc_amd_gpio gpio_set_stage_ram[] = {
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/* EC SCI# */
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PAD_SCI(GPIO_6, PULL_UP, EDGE_LOW),
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/* I2S SDIN */
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PAD_NF(GPIO_7, ACP_I2S_SDIN, PULL_NONE),
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/* I2S LRCLK */
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PAD_NF(GPIO_8, ACP_I2S_LRCLK, PULL_NONE),
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/* not Blink */
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PAD_GPI(GPIO_11, PULL_UP),
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/* APU_ALS_INT# */
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PAD_SCI(GPIO_24, PULL_UP, EDGE_LOW),
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/* SD card detect */
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PAD_GPI(GPIO_31, PULL_UP),
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/* NFC IRQ */
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PAD_INT(GPIO_69, PULL_UP, EDGE_LOW, STATUS),
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/* NFC wake output# */
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PAD_GPO(GPIO_89, HIGH),
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};
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void mainboard_program_gpios(void)
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{
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program_gpios(gpio_set_stage_ram, ARRAY_SIZE(gpio_set_stage_ram));
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}
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@ -0,0 +1,87 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <soc/platform_descriptors.h>
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#include <types.h>
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static const fsp_dxio_descriptor pollock_dxio_descriptors[] = {
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{ /* NVME SSD */
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.port_present = true,
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.engine_type = PCIE_ENGINE,
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.start_logical_lane = 0,
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.end_logical_lane = 0,
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.device_number = 1,
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.function_number = 3,
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.link_aspm = ASPM_L1,
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.link_aspm_L1_1 = true,
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.link_aspm_L1_2 = true,
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.turn_off_unused_lanes = true,
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.clk_req = CLK_REQ0
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},
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{ /* WWAN */
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.port_present = true,
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.engine_type = PCIE_ENGINE,
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.start_logical_lane = 1,
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.end_logical_lane = 1,
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.device_number = 1,
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.function_number = 4,
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.link_aspm = ASPM_L1,
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.link_aspm_L1_1 = true,
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.link_aspm_L1_2 = true,
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.turn_off_unused_lanes = true,
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.clk_req = CLK_REQ2
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},
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{ /* LAN */
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.port_present = true,
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.engine_type = PCIE_ENGINE,
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.start_logical_lane = 4,
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.end_logical_lane = 4,
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.device_number = 1,
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.function_number = 1,
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.link_aspm = ASPM_L1,
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.link_aspm_L1_1 = true,
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.link_aspm_L1_2 = true,
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.turn_off_unused_lanes = true,
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.clk_req = CLK_REQ1
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},
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{ /* WLAN */
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.port_present = true,
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||||
.engine_type = PCIE_ENGINE,
|
||||
.start_logical_lane = 5,
|
||||
.end_logical_lane = 5,
|
||||
.device_number = 1,
|
||||
.function_number = 2,
|
||||
.link_aspm = ASPM_L1,
|
||||
.link_aspm_L1_1 = true,
|
||||
.link_aspm_L1_2 = true,
|
||||
.turn_off_unused_lanes = true,
|
||||
.clk_req = CLK_REQ4
|
||||
}
|
||||
};
|
||||
|
||||
fsp_ddi_descriptor pollock_ddi_descriptors[] = {
|
||||
{ /* DDI0 - eDP */
|
||||
.connector_type = EDP,
|
||||
.aux_index = AUX1,
|
||||
.hdp_index = HDP1
|
||||
},
|
||||
{ /* DDI1 - DP */
|
||||
.connector_type = DP,
|
||||
.aux_index = AUX2,
|
||||
.hdp_index = HDP2
|
||||
},
|
||||
{ /* DDI2 - DP */
|
||||
.connector_type = DP,
|
||||
.aux_index = AUX4,
|
||||
.hdp_index = HDP4,
|
||||
}
|
||||
};
|
||||
|
||||
void mainboard_get_dxio_ddi_descriptors(
|
||||
const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num,
|
||||
const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num)
|
||||
{
|
||||
*dxio_descs = pollock_dxio_descriptors;
|
||||
*dxio_num = ARRAY_SIZE(pollock_dxio_descriptors);
|
||||
*ddi_descs = pollock_ddi_descriptors;
|
||||
*ddi_num = ARRAY_SIZE(pollock_ddi_descriptors);
|
||||
}
|
||||
Loading…
Reference in New Issue