From 407d552e0c642da601a88283676ee885402e81c4 Mon Sep 17 00:00:00 2001 From: Jonathan Zhang Date: Thu, 1 Oct 2020 14:20:41 -0700 Subject: [PATCH] vc/intel/fsp/fsp2_0/CPX-SP: update to Intel ww40 release Intel CPX-SP FSP ww40 release adds MeUmaEnable FSP-M parameter, and adds some fields to HOBs. Update FspmUpd.h and HOB header files. Signed-off-by: Jonathan Zhang Change-Id: I3d456be62a5feecdac267c1e8be52e2a25e8aac3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45940 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- .../intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h | 23 +++++++++++++++---- .../fsp/fsp2_0/cooperlake_sp/hob_iiouds.h | 1 + .../fsp/fsp2_0/cooperlake_sp/hob_memmap.h | 4 ++-- 3 files changed, 21 insertions(+), 7 deletions(-) diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h index 6bd0bc8b51..37ff1bd620 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h @@ -700,19 +700,32 @@ typedef struct { **/ UINT8 PchDciEn; -/** Offset 0x014D - SerialIoUartDebugEnable +/** Offset 0x014D - MeUmaEnable + Enable or disable ME UMA feature +**/ + UINT8 MeUmaEnable; + +/** Offset 0x014E - SerialIoUartDebugEnable Enable SerialIo Uart debug library in FSP. 0:Disable, 1:Enable **/ UINT8 SerialIoUartDebugEnable; -/** Offset 0x014E - ISA Serial Base selection +/** Offset 0x014F +**/ + UINT8 UnusedUpdSpace2; + +/** Offset 0x0150 - ISA Serial Base selection Select ISA Serial Base address could be initialized by boot loader. Default is 0x3F8 0x3F8, 0x2F8 **/ UINT16 SerialIoUartDebugIoBase; -/** Offset 0x0150 +/** Offset 0x0152 +**/ + UINT8 UnusedUpdSpace3[2]; + +/** Offset 0x0154 **/ UINT8 ReservedMemoryInitUpd[16]; } FSPM_CONFIG; @@ -733,9 +746,9 @@ typedef struct { **/ FSPM_CONFIG FspmConfig; -/** Offset 0x0160 +/** Offset 0x0164 **/ - UINT8 UnusedUpdSpace2[6]; + UINT8 UnusedUpdSpace4[2]; /** Offset 0x0166 **/ diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h index db39c3be3c..9900a121f2 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h @@ -209,6 +209,7 @@ typedef struct _STACK_RES { uint64_t PciResourceMem64Base; uint64_t PciResourceMem64Limit; uint32_t VtdBarAddress; + uint32_t Mmio32MinSize; // Minimum required size of MMIO32 resource needed for this stack } STACK_RES; typedef struct { diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h index 1229f1b427..7baa11a480 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h @@ -124,7 +124,7 @@ struct ChannelDevice { }; typedef struct socket { - UINT8 reserved1[1110]; + UINT8 reserved1[1114]; struct ChannelDevice ChannelInfo[MAX_CH]; } MEMMAP_SOCKET; @@ -154,7 +154,7 @@ typedef struct SystemMemoryMapHob { UINT32 MmiohBase; // MMIOH base in 64MB granularity - UINT8 reserved6[4]; + UINT8 reserved6[5]; } SYSTEM_MEMORY_MAP_HOB;