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include/cpu/msr.h: transform into an union 

This makes it easier to get the content of an msr into a full 64bit
variable.

Change-Id: I1b026cd3807fd68d805051a74b3d31fcde1c5626
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68572
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Arthur Heymans 2022-10-19 20:06:42 +02:00
parent 0c9fa6f2ce
commit 407e00dca0
4 changed files with 26 additions and 36 deletions
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2
src/cpu/x86/mtrr/earlymtrr.c
View File

@ -55,7 +55,7 @@ void set_var_mtrr(
void clear_all_var_mtrr(void) void clear_all_var_mtrr(void)
{ {
msr_t mtrr = {0, 0}; msr_t mtrr = { .raw = 0 };
int vcnt; int vcnt;
int i; int i;

13
src/include/cpu/x86/msr.h
View File

@ -285,7 +285,7 @@ static inline enum mca_err_code_types mca_err_type(msr_t reg)
static inline uint64_t msr_read(unsigned int reg) static inline uint64_t msr_read(unsigned int reg)
{ {
msr_t msr = rdmsr(reg); msr_t msr = rdmsr(reg);
return (((uint64_t)msr.hi << 32) | msr.lo); return msr.raw;
} }
/** /**
@ -296,10 +296,7 @@ static inline uint64_t msr_read(unsigned int reg)
*/ */
static inline void msr_write(unsigned int reg, uint64_t value) static inline void msr_write(unsigned int reg, uint64_t value)
{ {
msr_t msr = { msr_t msr = { .raw = value };
.lo = (unsigned int)value,
.hi = (unsigned int)(value >> 32)
};
wrmsr(reg, msr); wrmsr(reg, msr);
} }
@ -315,10 +312,8 @@ static inline void msr_unset_and_set(unsigned int reg, uint64_t unset, uint64_t
msr_t msr; msr_t msr;
msr = rdmsr(reg); msr = rdmsr(reg);
msr.lo &= (unsigned int)~unset; msr.raw &= ~unset;
msr.hi &= (unsigned int)~(unset >> 32); msr.raw |= set;
msr.lo |= (unsigned int)set;
msr.hi |= (unsigned int)(set >> 32);
wrmsr(reg, msr); wrmsr(reg, msr);
} }

10
src/include/cpu/x86/msr_access.h
View File

@ -6,10 +6,14 @@
#ifndef __ASSEMBLER__ #ifndef __ASSEMBLER__
#include <types.h> #include <types.h>
typedef struct msr_struct { typedef union msr_union {
unsigned int lo; struct {
unsigned int hi; unsigned int lo;
unsigned int hi;
};
uint64_t raw;
} msr_t; } msr_t;
_Static_assert(sizeof(msr_t) == sizeof(uint64_t), "Incorrect size for msr_t");
#if CONFIG(SOC_SETS_MSRS) #if CONFIG(SOC_SETS_MSRS)
msr_t soc_msr_read(unsigned int index); msr_t soc_msr_read(unsigned int index);

37
src/soc/intel/common/block/sgx/sgx.c
View File

@ -24,14 +24,7 @@ int is_sgx_supported(void)
void prmrr_core_configure(void) void prmrr_core_configure(void)
{ {
union { msr_t prmrr_base, prmrr_mask;
uint64_t data64;
struct {
uint32_t lo;
uint32_t hi;
} data32;
} prmrr_base, prmrr_mask;
msr_t msr;
/* /*
* Software Developer's Manual Volume 4: * Software Developer's Manual Volume 4:
@ -45,38 +38,36 @@ void prmrr_core_configure(void)
return; return;
/* PRMRR_PHYS_MASK is in scope "Core" */ /* PRMRR_PHYS_MASK is in scope "Core" */
msr = rdmsr(MSR_PRMRR_PHYS_MASK); prmrr_mask = rdmsr(MSR_PRMRR_PHYS_MASK);
/* If it is locked don't attempt to write PRMRR MSRs. */ /* If it is locked don't attempt to write PRMRR MSRs. */
if (msr.lo & PRMRR_PHYS_MASK_LOCK) if (prmrr_mask.lo & PRMRR_PHYS_MASK_LOCK)
return; return;
/* PRMRR base and mask are read from the UNCORE PRMRR MSRs /* PRMRR base and mask are read from the UNCORE PRMRR MSRs
* that are already set in FSP-M. */ * that are already set in FSP-M. */
if (soc_get_uncore_prmmr_base_and_mask(&prmrr_base.data64, if (soc_get_uncore_prmmr_base_and_mask(&prmrr_base.raw,
&prmrr_mask.data64) < 0) { &prmrr_mask.raw) < 0) {
printk(BIOS_ERR, "SGX: Failed to get PRMRR base and mask\n"); printk(BIOS_ERR, "SGX: Failed to get PRMRR base and mask\n");
return; return;
} }
if (!prmrr_base.data32.lo) { if (!prmrr_base.lo) {
printk(BIOS_ERR, "SGX Error: Uncore PRMRR is not set!\n"); printk(BIOS_ERR, "SGX Error: Uncore PRMRR is not set!\n");
return; return;
} }
printk(BIOS_INFO, "SGX: prmrr_base = 0x%llx\n", prmrr_base.data64); printk(BIOS_INFO, "SGX: prmrr_base = 0x%llx\n", prmrr_base.raw);
printk(BIOS_INFO, "SGX: prmrr_mask = 0x%llx\n", prmrr_mask.data64); printk(BIOS_INFO, "SGX: prmrr_mask = 0x%llx\n", prmrr_mask.raw);
/* Program core PRMRR MSRs. /* Program core PRMRR MSRs.
* - Set cache writeback mem attrib in PRMRR base MSR * - Set cache writeback mem attrib in PRMRR base MSR
* - Clear the valid bit in PRMRR mask MSR * - Clear the valid bit in PRMRR mask MSR
* - Lock PRMRR MASK MSR */ * - Lock PRMRR MASK MSR */
prmrr_base.data32.lo |= MTRR_TYPE_WRBACK; prmrr_base.lo |= MTRR_TYPE_WRBACK;
wrmsr(MSR_PRMRR_PHYS_BASE, (msr_t) {.lo = prmrr_base.data32.lo, wrmsr(MSR_PRMRR_PHYS_BASE, prmrr_base);
.hi = prmrr_base.data32.hi}); prmrr_mask.lo &= ~PRMRR_PHYS_MASK_VALID;
prmrr_mask.data32.lo &= ~PRMRR_PHYS_MASK_VALID; prmrr_mask.lo |= PRMRR_PHYS_MASK_LOCK;
prmrr_mask.data32.lo |= PRMRR_PHYS_MASK_LOCK; wrmsr(MSR_PRMRR_PHYS_MASK, prmrr_mask);
wrmsr(MSR_PRMRR_PHYS_MASK, (msr_t) {.lo = prmrr_mask.data32.lo,
.hi = prmrr_mask.data32.hi});
} }
static int is_prmrr_set(void) static int is_prmrr_set(void)
@ -133,7 +124,7 @@ static int owner_epoch_update(void)
{ {
/* TODO - the Owner Epoch update mechanism is not determined yet, /* TODO - the Owner Epoch update mechanism is not determined yet,
* for PoC just write '0's to the MSRs. */ * for PoC just write '0's to the MSRs. */
msr_t msr = {0, 0}; msr_t msr = { .raw = 0 };
/* SGX_OWNEREPOCH is in scope "Package" */ /* SGX_OWNEREPOCH is in scope "Package" */
wrmsr(MSR_SGX_OWNEREPOCH0, msr); wrmsr(MSR_SGX_OWNEREPOCH0, msr);