mb/intel/adlrvp_m: Add initial code for adl-m variant board
List of changes: 1. Add mainboard Kconfig to Kconfig.name files 2. Handle mainboard names in Kconfig file for adlrvp 3. Created a new devicetree.cb for Adlrvp-m. 3. Add override devicetree for ADL-M RVP. 4. Configure proper PCI and USB ports as per schematics for ADL-M BUG=None BRANCH=None TEST=Able to build ADL-M RVP variants adlrvp_m and adlrvp_m_ext_ec. Signed-0ff-by: Maulik Vaghela <maulik.v.vaghela@intel.com> Signed-off-by: Varshit Pandya <varshit.b.pandya@intel.com> Change-Id: I997b89ba87fb03dfa6a836caec51efd05baa2e8d Reviewed-on: https://review.coreboot.org/c/coreboot/+/49871 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Varshit Pandya
Patrick Georgi
parent
7eac884bad
commit
4084702567
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@ -1,4 +1,4 @@
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if BOARD_INTEL_ADLRVP_P || BOARD_INTEL_ADLRVP_P_EXT_EC
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if BOARD_INTEL_ADLRVP_P || BOARD_INTEL_ADLRVP_P_EXT_EC || BOARD_INTEL_ADLRVP_M || BOARD_INTEL_ADLRVP_M_EXT_EC
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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@ -9,10 +9,11 @@ config BOARD_SPECIFIC_OPTIONS
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select DRIVERS_I2C_HID
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select DRIVERS_I2C_GENERIC
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select DRIVERS_INTEL_SOUNDWIRE
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select DRIVERS_INTEL_PMC if BOARD_INTEL_ADLRVP_P_EXT_EC
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select DRIVERS_INTEL_PMC if BOARD_INTEL_ADLRVP_P_EXT_EC || BOARD_INTEL_ADLRVP_M_EXT_EC
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select DRIVERS_USB_ACPI
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select DRIVERS_SPI_ACPI
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select SOC_INTEL_ALDERLAKE
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select SOC_INTEL_ALDERLAKE_PCH_M if BOARD_INTEL_ADLRVP_M || BOARD_INTEL_ADLRVP_M_EXT_EC
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select HAVE_SPD_IN_CBFS
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select DRIVERS_SOUNDWIRE_ALC711
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select PCIEXP_HOTPLUG
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@ -33,10 +34,13 @@ config VARIANT_DIR
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string
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default "adlrvp_p" if BOARD_INTEL_ADLRVP_P
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default "adlrvp_p_ext_ec" if BOARD_INTEL_ADLRVP_P_EXT_EC
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default "adlrvp_m" if BOARD_INTEL_ADLRVP_M
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default "adlrvp_m_ext_ec" if BOARD_INTEL_ADLRVP_M_EXT_EC
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config GBB_HWID
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string
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depends on CHROMEOS
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default "ADLRVPM" if BOARD_INTEL_ADLRVP_M || BOARD_INTEL_ADLRVP_M_EXT_EC
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default "ADLRVPP"
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config MAINBOARD_PART_NUMBER
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@ -47,6 +51,11 @@ config MAINBOARD_FAMILY
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string
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default "Intel_adlrvp"
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config DEVICETREE
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string
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default "devicetree_m.cb" if BOARD_INTEL_ADLRVP_M || BOARD_INTEL_ADLRVP_M_EXT_EC
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default "devicetree.cb"
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config OVERRIDE_DEVICETREE
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string
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default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
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@ -57,8 +66,8 @@ config DIMM_SPD_SIZE
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choice
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prompt "ON BOARD EC"
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default ADL_INTEL_EC if BOARD_INTEL_ADLRVP_P
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default ADL_CHROME_EC if BOARD_INTEL_ADLRVP_P_EXT_EC
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default ADL_INTEL_EC if BOARD_INTEL_ADLRVP_P || BOARD_INTEL_ADLRVP_M
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default ADL_CHROME_EC if BOARD_INTEL_ADLRVP_P_EXT_EC || BOARD_INTEL_ADLRVP_M_EXT_EC
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help
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This option allows you to select the on board EC to use.
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Select whether the board has Intel EC or Chrome EC
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@ -6,3 +6,12 @@ config BOARD_INTEL_ADLRVP_P
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config BOARD_INTEL_ADLRVP_P_EXT_EC
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bool "Alderlake-P RVP with Chrome EC"
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select INTEL_LPSS_UART_FOR_CONSOLE
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config BOARD_INTEL_ADLRVP_M
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bool "Alderlake-M RVP"
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select DRIVERS_UART_8250IO
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select MAINBOARD_USES_IFD_EC_REGION
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config BOARD_INTEL_ADLRVP_M_EXT_EC
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bool "Alderlake-M RVP with Chrome EC"
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select INTEL_LPSS_UART_FOR_CONSOLE
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@ -0,0 +1,265 @@
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chip soc/intel/alderlake
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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# GPE configuration
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# Note that GPE events called out in ASL code rely on this
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# route. i.e. If this route changes then the affected GPE
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# offset bits also need to be changed.
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register "pmc_gpe0_dw0" = "GPP_B"
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register "pmc_gpe0_dw1" = "GPP_D"
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register "pmc_gpe0_dw2" = "GPP_E"
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# FSP configuration
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register "usb2_ports[0]" = "USB2_PORT_MID(OC1)" # Type-C port 0
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register "usb2_ports[1]" = "USB2_PORT_MID(OC1)" # Type-C port 1
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register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WLAN
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register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN
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register "usb2_ports[4]" = "USB2_PORT_MID(OC2)" # Type-A port 1
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register "usb2_ports[5]" = "USB2_PORT_MID(OC2)" # Type-A port 2
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register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port1
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register "usb2_ports[7]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port2
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register "usb2_ports[8]" = "USB2_PORT_MID(OC3)" # USB3/2 Type A port3
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register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
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register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # Type-A port 1
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register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)" # Type-A port 2
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register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WWAN
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register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WLAN
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# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
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register "gen1_dec" = "0x00fc0801"
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register "gen2_dec" = "0x000c0201"
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# EC memory map range is 0x900-0x9ff
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register "gen3_dec" = "0x00fc0901"
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register "gen4_dec" = "0x000c0081"
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register "PrmrrSize" = "0"
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#Enable PCH PCIE RP 4 using CLK 5
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register "pch_pcie_rp[PCH_RP(4)]" = "{
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.clk_src = 5,
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.clk_req = 5,
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.flags = PCIE_RP_CLK_REQ_DETECT,
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}"
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# Enable PCH PCIE RP 5 using CLK 2
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register "pch_pcie_rp[PCH_RP(5)]" = "{
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.clk_src = 2,
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.clk_req = 2,
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.flags = PCIE_RP_CLK_REQ_DETECT,
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}"
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# Enable PCH PCIE RP 9 using CLK 3
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register "pch_pcie_rp[PCH_RP(9)]" = "{
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.clk_src = 3,
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.clk_req = 3,
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.flags = PCIE_RP_CLK_REQ_DETECT,
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}"
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#Enable PCH PCIE RP 10 using CLK 1
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register "pch_pcie_rp[PCH_RP(10)]" = "{
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.clk_src = 1,
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.clk_req = 1,
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.flags = PCIE_RP_CLK_REQ_DETECT,
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}"
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# Hybrid storage mode
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register "HybridStorageMode" = "1"
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# Enable CPU PCIE RP 1 using CLK 0
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register "cpu_pcie_rp[CPU_RP(1)]" = "{
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.clk_req = 0,
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.clk_src = 0,
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}"
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# Enable EDP in PortA
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register "DdiPortAConfig" = "1"
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# Enable HDMI in Port B
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register "DdiPortBDdc" = "1"
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register "DdiPortBHpd" = "1"
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# TCSS USB3
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register "TcssAuxOri" = "0"
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register "s0ix_enable" = "1"
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register "SerialIoI2cMode" = "{
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[PchSerialIoIndexI2C0] = PchSerialIoPci,
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[PchSerialIoIndexI2C1] = PchSerialIoPci,
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[PchSerialIoIndexI2C2] = PchSerialIoDisabled,
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[PchSerialIoIndexI2C3] = PchSerialIoDisabled,
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[PchSerialIoIndexI2C4] = PchSerialIoDisabled,
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[PchSerialIoIndexI2C5] = PchSerialIoPci,
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}"
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register "SerialIoGSpiMode" = "{
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[PchSerialIoIndexGSPI0] = PchSerialIoPci,
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[PchSerialIoIndexGSPI1] = PchSerialIoDisabled,
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[PchSerialIoIndexGSPI2] = PchSerialIoDisabled,
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[PchSerialIoIndexGSPI3] = PchSerialIoDisabled,
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}"
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register "SerialIoGSpiCsMode" = "{
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[PchSerialIoIndexGSPI0] = 0,
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[PchSerialIoIndexGSPI1] = 0,
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[PchSerialIoIndexGSPI2] = 0,
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[PchSerialIoIndexGSPI3] = 0,
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}"
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register "SerialIoGSpiCsState" = "{
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[PchSerialIoIndexGSPI0] = 0,
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[PchSerialIoIndexGSPI1] = 0,
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[PchSerialIoIndexGSPI2] = 0,
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[PchSerialIoIndexGSPI3] = 0,
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}"
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register "SerialIoUartMode" = "{
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[PchSerialIoIndexUART0] = PchSerialIoSkipInit,
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[PchSerialIoIndexUART1] = PchSerialIoDisabled,
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[PchSerialIoIndexUART2] = PchSerialIoDisabled,
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}"
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# HD Audio
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register "PchHdaDspEnable" = "1"
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register "PchHdaAudioLinkHdaEnable" = "0"
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register "PchHdaAudioLinkDmicEnable[0]" = "1"
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register "PchHdaAudioLinkDmicEnable[1]" = "1"
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register "PchHdaAudioLinkSndwEnable[0]" = "1"
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register "PchHdaAudioLinkSndwEnable[1]" = "1"
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# iDisp-Link T-Mode 0: 2T, 2: 4T, 3: 8T, 4: 16T
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register "PchHdaIDispLinkTmode" = "2"
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# iDisp-Link Freq 4: 96MHz, 3: 48MHz.
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register "PchHdaIDispLinkFrequency" = "4"
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# Not disconnected/enumerable
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register "PchHdaIDispCodecDisconnect" = "0"
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# Intel Common SoC Config
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register "common_soc_config" = "{
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.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
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.i2c[0] = {
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.speed = I2C_SPEED_FAST,
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},
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.i2c[1] = {
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.speed = I2C_SPEED_FAST,
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},
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.i2c[2] = {
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.speed = I2C_SPEED_FAST,
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},
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.i2c[3] = {
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.speed = I2C_SPEED_FAST,
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},
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.i2c[5] = {
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.speed = I2C_SPEED_FAST,
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},
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}"
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device domain 0 on
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device pci 00.0 on end # Host Bridge
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device pci 01.0 on end # PEG10
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device pci 02.0 on end # Graphics
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device pci 04.0 on end # DPTF
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device pci 05.0 on end # IPU
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device pci 06.0 on end # PEG60
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device pci 06.2 on end # PEG62
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device pci 07.0 on end # TBT_PCIe0
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device pci 07.1 on end # TBT_PCIe1
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device pci 07.2 on end # TBT_PCIe2
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device pci 07.3 on end # TBT_PCIe3
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device pci 08.0 off end # GNA
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device pci 09.0 off end # NPK
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device pci 0a.0 off end # Crash-log SRAM
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device pci 0d.0 on end # USB xHCI
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device pci 0d.1 on end # USB xDCI (OTG)
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device pci 0d.2 on end # TBT DMA0
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device pci 0d.3 on end # TBT DMA1
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device pci 0e.0 off end # VMD
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device pci 10.0 off end
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device pci 10.1 off end
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device pci 10.2 on end # CNVi: BT
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device pci 10.6 off end # THC0
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device pci 10.7 off end # THC1
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device pci 11.0 off end
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device pci 11.1 off end
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device pci 11.2 off end
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device pci 11.3 off end
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device pci 11.4 off end
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device pci 11.5 off end
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device pci 12.0 off end # SensorHUB
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device pci 12.5 off end
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device pci 12.6 off end # GSPI2
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device pci 13.0 off end # GSPI3
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device pci 13.1 off end
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device pci 14.0 on
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chip drivers/usb/acpi
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register "desc" = ""Root Hub""
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register "type" = "UPC_TYPE_HUB"
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device usb 0.0 on
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chip drivers/usb/acpi
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register "desc" = ""Bluetooth""
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register "type" = "UPC_TYPE_INTERNAL"
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device usb 2.9 on end
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end
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end
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end
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end # USB3.1 xHCI
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device pci 14.1 off end # USB3.1 xDCI
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device pci 14.2 off end # Shared RAM
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device pci 14.3 on
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chip drivers/wifi/generic
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register "wake" = "GPE0_PME_B0"
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device generic 0 on end
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end
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end # CNVi: WiFi
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device pci 15.0 on end # I2C0
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device pci 15.1 on end # I2C1
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device pci 15.2 on end # I2C2
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device pci 15.3 on end # I2C3
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device pci 16.0 on end # HECI1
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device pci 16.1 off end # HECI2
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device pci 16.2 off end # CSME
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device pci 16.3 off end # CSME
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device pci 16.4 off end # HECI3
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device pci 16.5 off end # HECI4
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device pci 17.0 on end # SATA
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device pci 19.0 off end # I2C4
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device pci 19.1 on end # I2C5
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device pci 19.2 off end # UART2
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device pci 1c.0 on end # RP1
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device pci 1c.1 off end # RP2
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device pci 1c.2 on end # RP3 # W/A to FSP issue
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device pci 1c.3 on end # RP4 # W/A to FSP issue
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device pci 1c.4 on end # RP5
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device pci 1c.5 on end # RP6
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device pci 1c.6 off end # RP7
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device pci 1c.7 on end # RP8
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device pci 1d.0 on end # RP9
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device pci 1d.1 on end # RP10
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device pci 1d.2 off end # RP11
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device pci 1d.3 off end # RP12
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device pci 1e.0 on end # UART0
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device pci 1e.1 off end # UART1
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device pci 1e.2 on end # GSPI0
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device pci 1e.3 off end # GSPI1
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device pci 1f.0 on end # eSPI
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device pci 1f.1 on end # P2SB
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device pci 1f.2 hidden end # PMC
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device pci 1f.3 on
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chip drivers/intel/soundwire
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device generic 0 on
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chip drivers/soundwire/alc711
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# SoundWire Link 0 ID 1
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register "desc" = ""Headset Codec""
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device generic 0.1 on end
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end
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end
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end
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end # Intel Audio SNDW
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device pci 1f.4 on end # SMBus
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device pci 1f.5 on end # SPI
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device pci 1f.6 off end # GbE
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device pci 1f.7 off end # TH
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end
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end
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@ -0,0 +1,3 @@
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chip soc/intel/alderlake
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device domain 0 on end
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end
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@ -0,0 +1,27 @@
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chip soc/intel/alderlake
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device domain 0 on
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device pci 1f.2 hidden
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# The pmc_mux chip driver is a placeholder for the
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# PMC.MUX device in the ACPI hierarchy.
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chip drivers/intel/pmc_mux
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device generic 0 on
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chip drivers/intel/pmc_mux/conn
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register "usb2_port_number" = "1"
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register "usb3_port_number" = "1"
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# SBU is fixed, HSL follows CC
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register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL"
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device generic 0 alias conn0 on end
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end
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chip drivers/intel/pmc_mux/conn
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register "usb2_port_number" = "2"
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register "usb3_port_number" = "2"
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# SBU is fixed, HSL follows CC
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register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL"
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device generic 1 alias conn1 on end
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end
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end
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end
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end # PMC
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end
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end
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