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mb/**/dsdt.asl: Remove outdated sleepstates.asl comment 

Previously, each Intel chipset had its own sleepstates.asl file.
However, this is no longer the case, so drop these comments.

Change-Id: I50aba6e74f41e2fa498375b5eb6b7e993d06bcac
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37855
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This commit is contained in:
Angel Pons 2019-12-19 22:41:06 +01:00 committed by Patrick Georgi
parent ae863e2e25
commit 408d1dac9e
86 changed files with 3 additions and 86 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
src/mainboard/apple/macbook21/dsdt.asl
View File

@ -44,6 +44,5 @@ DefinitionBlock(
} }
} }
/* Chipset specific sleep states */
#include <southbridge/intel/common/acpi/sleepstates.asl> #include <southbridge/intel/common/acpi/sleepstates.asl>
} }

1
src/mainboard/asrock/g41c-gs/dsdt.asl
View File

@ -37,6 +37,5 @@ DefinitionBlock(
} }
} }
/* Chipset specific sleep states */
#include <southbridge/intel/common/acpi/sleepstates.asl> #include <southbridge/intel/common/acpi/sleepstates.asl>
} }

1
src/mainboard/asrock/h110m/dsdt.asl
View File

@ -47,7 +47,6 @@ DefinitionBlock(
#include "acpi/dptf.asl" #include "acpi/dptf.asl"
} }
// Chipset specific sleep states
#include <southbridge/intel/common/acpi/sleepstates.asl> #include <southbridge/intel/common/acpi/sleepstates.asl>
// Mainboard specific // Mainboard specific

1
src/mainboard/asus/p5gc-mx/dsdt.asl
View File

@ -48,6 +48,5 @@ DefinitionBlock(
} }
} }
/* Chipset specific sleep states */
#include <southbridge/intel/common/acpi/sleepstates.asl> #include <southbridge/intel/common/acpi/sleepstates.asl>
} }

1
src/mainboard/asus/p5qc/dsdt.asl
View File

@ -37,6 +37,5 @@ DefinitionBlock(
} }
} }
/* Chipset specific sleep states */
#include <southbridge/intel/common/acpi/sleepstates.asl> #include <southbridge/intel/common/acpi/sleepstates.asl>
} }

1
src/mainboard/asus/p5ql-em/dsdt.asl
View File

@ -36,6 +36,5 @@ DefinitionBlock(
} }
} }
/* Chipset specific sleep states */
#include <southbridge/intel/common/acpi/sleepstates.asl> #include <southbridge/intel/common/acpi/sleepstates.asl>
} }

1
src/mainboard/asus/p5qpl-am/dsdt.asl
View File

@ -37,6 +37,5 @@ DefinitionBlock(
} }
} }
/* Chipset specific sleep states */
#include <southbridge/intel/common/acpi/sleepstates.asl> #include <southbridge/intel/common/acpi/sleepstates.asl>
} }

2
src/mainboard/facebook/fbg1701/dsdt.asl
View File

@ -43,7 +43,7 @@ DefinitionBlock(
} }
} }
/* Chipset specific sleep states */ /* Mainboard specific sleep states */
#include "acpi/sleepstates.asl" #include "acpi/sleepstates.asl"
#include "acpi/mainboard.asl" #include "acpi/mainboard.asl"
} }

1
src/mainboard/facebook/monolith/dsdt.asl
View File

@ -45,7 +45,6 @@ DefinitionBlock(
#include "acpi/dptf.asl" #include "acpi/dptf.asl"
} }
// Chipset specific sleep states
#include <southbridge/intel/common/acpi/sleepstates.asl> #include <southbridge/intel/common/acpi/sleepstates.asl>
// Mainboard specific // Mainboard specific

1
src/mainboard/foxconn/d41s/dsdt.asl
View File

@ -37,6 +37,5 @@ DefinitionBlock(
} }
} }
/* Chipset specific sleep states */
#include <southbridge/intel/common/acpi/sleepstates.asl> #include <southbridge/intel/common/acpi/sleepstates.asl>
} }

1
src/mainboard/foxconn/g41s-k/dsdt.asl
View File

@ -37,6 +37,5 @@ DefinitionBlock(
} }
} }
/* Chipset specific sleep states */
#include <southbridge/intel/common/acpi/sleepstates.asl> #include <southbridge/intel/common/acpi/sleepstates.asl>
} }

1
src/mainboard/getac/p470/dsdt.asl
View File

@ -53,6 +53,5 @@ DefinitionBlock(
} }
} }
/* Chipset specific sleep states */
#include <southbridge/intel/common/acpi/sleepstates.asl> #include <southbridge/intel/common/acpi/sleepstates.asl>
} }

1
src/mainboard/gigabyte/ga-945gcm-s2l/dsdt.asl
View File

@ -48,6 +48,5 @@ DefinitionBlock(
} }
} }
/* Chipset specific sleep states */
#include <southbridge/intel/common/acpi/sleepstates.asl> #include <southbridge/intel/common/acpi/sleepstates.asl>
} }

1
src/mainboard/gigabyte/ga-g41m-es2l/dsdt.asl
View File

@ -37,6 +37,5 @@ DefinitionBlock(
} }
} }
/* Chipset specific sleep states */
#include <southbridge/intel/common/acpi/sleepstates.asl> #include <southbridge/intel/common/acpi/sleepstates.asl>
} }

1
src/mainboard/google/auron/dsdt.asl
View File

@ -49,7 +49,6 @@ DefinitionBlock(
// Chrome OS specific // Chrome OS specific
#include <vendorcode/google/chromeos/acpi/chromeos.asl> #include <vendorcode/google/chromeos/acpi/chromeos.asl>
// Chipset specific sleep states
#include <southbridge/intel/common/acpi/sleepstates.asl> #include <southbridge/intel/common/acpi/sleepstates.asl>
// Mainboard specific // Mainboard specific

1
src/mainboard/google/beltino/dsdt.asl
View File

@ -51,6 +51,5 @@ DefinitionBlock(
// Chrome OS specific // Chrome OS specific
#include <vendorcode/google/chromeos/acpi/chromeos.asl> #include <vendorcode/google/chromeos/acpi/chromeos.asl>
// Chipset specific sleep states
#include <southbridge/intel/common/acpi/sleepstates.asl> #include <southbridge/intel/common/acpi/sleepstates.asl>
} }

1
src/mainboard/google/butterfly/dsdt.asl
View File

@ -52,6 +52,5 @@ DefinitionBlock(
#include <vendorcode/google/chromeos/acpi/chromeos.asl> #include <vendorcode/google/chromeos/acpi/chromeos.asl>
/* Chipset specific sleep states */
#include <southbridge/intel/common/acpi/sleepstates.asl> #include <southbridge/intel/common/acpi/sleepstates.asl>
} }

1
src/mainboard/google/cyan/dsdt.asl
View File

@ -60,7 +60,6 @@ DefinitionBlock(
} }
#include <vendorcode/google/chromeos/acpi/chromeos.asl> #include <vendorcode/google/chromeos/acpi/chromeos.asl>
/* Chipset specific sleep states */
#include <southbridge/intel/common/acpi/sleepstates.asl> #include <southbridge/intel/common/acpi/sleepstates.asl>
#include "acpi/mainboard.asl" #include "acpi/mainboard.asl"

1
src/mainboard/google/dragonegg/dsdt.asl
View File

@ -47,7 +47,6 @@ DefinitionBlock(
#include <vendorcode/google/chromeos/acpi/chromeos.asl> #include <vendorcode/google/chromeos/acpi/chromeos.asl>
#endif #endif
// Chipset specific sleep states
#include <southbridge/intel/common/acpi/sleepstates.asl> #include <southbridge/intel/common/acpi/sleepstates.asl>
/* Chrome OS Embedded Controller */ /* Chrome OS Embedded Controller */

1
src/mainboard/google/drallion/dsdt.asl
View File

@ -52,7 +52,6 @@ DefinitionBlock(
#include <vendorcode/google/chromeos/acpi/amac.asl> #include <vendorcode/google/chromeos/acpi/amac.asl>
#endif #endif
/* Chipset specific sleep states */
#include <southbridge/intel/common/acpi/sleepstates.asl> #include <southbridge/intel/common/acpi/sleepstates.asl>
/* Low power idle table */ /* Low power idle table */

1
src/mainboard/google/eve/dsdt.asl
View File

@ -46,7 +46,6 @@ DefinitionBlock(
/* Chrome OS specific */ /* Chrome OS specific */
#include <vendorcode/google/chromeos/acpi/chromeos.asl> #include <vendorcode/google/chromeos/acpi/chromeos.asl>
/* Chipset specific sleep states */
#include <southbridge/intel/common/acpi/sleepstates.asl> #include <southbridge/intel/common/acpi/sleepstates.asl>
/* Chrome OS Embedded Controller */ /* Chrome OS Embedded Controller */

1
src/mainboard/google/fizz/dsdt.asl
View File

@ -46,7 +46,6 @@ DefinitionBlock(
/* Chrome OS specific */ /* Chrome OS specific */
#include <vendorcode/google/chromeos/acpi/chromeos.asl> #include <vendorcode/google/chromeos/acpi/chromeos.asl>
/* Chipset specific sleep states */
#include <southbridge/intel/common/acpi/sleepstates.asl> #include <southbridge/intel/common/acpi/sleepstates.asl>
/* Chrome OS Embedded Controller */ /* Chrome OS Embedded Controller */

1
src/mainboard/google/glados/dsdt.asl
View File

@ -47,7 +47,6 @@ DefinitionBlock(
// Chrome OS specific // Chrome OS specific
#include <vendorcode/google/chromeos/acpi/chromeos.asl> #include <vendorcode/google/chromeos/acpi/chromeos.asl>
// Chipset specific sleep states
#include <southbridge/intel/common/acpi/sleepstates.asl> #include <southbridge/intel/common/acpi/sleepstates.asl>
// Mainboard specific // Mainboard specific

1
src/mainboard/google/hatch/dsdt.asl
View File

@ -47,7 +47,6 @@ DefinitionBlock(
#include <vendorcode/google/chromeos/acpi/chromeos.asl> #include <vendorcode/google/chromeos/acpi/chromeos.asl>
#endif #endif
/* Chipset specific sleep states */
#include <southbridge/intel/common/acpi/sleepstates.asl> #include <southbridge/intel/common/acpi/sleepstates.asl>
/* Low power idle table */ /* Low power idle table */

1
src/mainboard/google/jecht/dsdt.asl
View File

@ -50,7 +50,6 @@ DefinitionBlock(
// Chrome OS specific // Chrome OS specific
#include <vendorcode/google/chromeos/acpi/chromeos.asl> #include <vendorcode/google/chromeos/acpi/chromeos.asl>
// Chipset specific sleep states
#include <southbridge/intel/common/acpi/sleepstates.asl> #include <southbridge/intel/common/acpi/sleepstates.asl>
// Mainboard specific // Mainboard specific

1
src/mainboard/google/link/dsdt.asl
View File

@ -53,6 +53,5 @@ DefinitionBlock(
#include <vendorcode/google/chromeos/acpi/chromeos.asl> #include <vendorcode/google/chromeos/acpi/chromeos.asl>
/* Chipset specific sleep states */
#include <southbridge/intel/common/acpi/sleepstates.asl> #include <southbridge/intel/common/acpi/sleepstates.asl>
} }

1
src/mainboard/google/octopus/dsdt.asl
View File

@ -44,7 +44,6 @@ DefinitionBlock(
/* Chrome OS specific */ /* Chrome OS specific */
#include <vendorcode/google/chromeos/acpi/chromeos.asl> #include <vendorcode/google/chromeos/acpi/chromeos.asl>
/* Chipset specific sleep states */
#include <southbridge/intel/common/acpi/sleepstates.asl> #include <southbridge/intel/common/acpi/sleepstates.asl>
/* Chrome OS Embedded Controller */ /* Chrome OS Embedded Controller */

1
src/mainboard/google/parrot/dsdt.asl
View File

@ -53,6 +53,5 @@ DefinitionBlock(
#include <vendorcode/google/chromeos/acpi/chromeos.asl> #include <vendorcode/google/chromeos/acpi/chromeos.asl>
/* Chipset specific sleep states */
#include <southbridge/intel/common/acpi/sleepstates.asl> #include <southbridge/intel/common/acpi/sleepstates.asl>
} }

1
src/mainboard/google/poppy/dsdt.asl
View File

@ -53,7 +53,6 @@ DefinitionBlock(
/* Chrome OS specific */ /* Chrome OS specific */
#include <vendorcode/google/chromeos/acpi/chromeos.asl> #include <vendorcode/google/chromeos/acpi/chromeos.asl>
/* Chipset specific sleep states */
#include <southbridge/intel/common/acpi/sleepstates.asl> #include <southbridge/intel/common/acpi/sleepstates.asl>
/* Chrome OS Embedded Controller */ /* Chrome OS Embedded Controller */

1
src/mainboard/google/rambi/dsdt.asl
View File

@ -46,7 +46,6 @@ DefinitionBlock(
#include <vendorcode/google/chromeos/acpi/chromeos.asl> #include <vendorcode/google/chromeos/acpi/chromeos.asl>
/* Chipset specific sleep states */
#include <southbridge/intel/common/acpi/sleepstates.asl> #include <southbridge/intel/common/acpi/sleepstates.asl>
#include "acpi/mainboard.asl" #include "acpi/mainboard.asl"

1
src/mainboard/google/reef/dsdt.asl
View File

@ -44,7 +44,6 @@ DefinitionBlock(
/* Chrome OS specific */ /* Chrome OS specific */
#include <vendorcode/google/chromeos/acpi/chromeos.asl> #include <vendorcode/google/chromeos/acpi/chromeos.asl>
/* Chipset specific sleep states */
#include <southbridge/intel/common/acpi/sleepstates.asl> #include <southbridge/intel/common/acpi/sleepstates.asl>
/* Chrome OS Embedded Controller */ /* Chrome OS Embedded Controller */

1
src/mainboard/google/sarien/dsdt.asl
View File

@ -52,7 +52,6 @@ DefinitionBlock(
#include <vendorcode/google/chromeos/acpi/amac.asl> #include <vendorcode/google/chromeos/acpi/amac.asl>
#endif #endif
/* Chipset specific sleep states */
#include <southbridge/intel/common/acpi/sleepstates.asl> #include <southbridge/intel/common/acpi/sleepstates.asl>
/* Low power idle table */ /* Low power idle table */

1
src/mainboard/google/slippy/dsdt.asl
View File

@ -62,6 +62,5 @@ DefinitionBlock(
// Chrome OS specific // Chrome OS specific
#include <vendorcode/google/chromeos/acpi/chromeos.asl> #include <vendorcode/google/chromeos/acpi/chromeos.asl>
// Chipset specific sleep states
#include <southbridge/intel/common/acpi/sleepstates.asl> #include <southbridge/intel/common/acpi/sleepstates.asl>
} }

1
src/mainboard/google/stout/dsdt.asl
View File

@ -53,6 +53,5 @@ DefinitionBlock(
#include <vendorcode/google/chromeos/acpi/chromeos.asl> #include <vendorcode/google/chromeos/acpi/chromeos.asl>
/* Chipset specific sleep states */
#include <southbridge/intel/common/acpi/sleepstates.asl> #include <southbridge/intel/common/acpi/sleepstates.asl>
} }

1
src/mainboard/ibase/mb899/dsdt.asl
View File

@ -45,6 +45,5 @@ DefinitionBlock(
} }
} }
/* Chipset specific sleep states */
#include <southbridge/intel/common/acpi/sleepstates.asl> #include <southbridge/intel/common/acpi/sleepstates.asl>
} }

1
src/mainboard/intel/apollolake_rvp/dsdt.asl
View File

@ -32,7 +32,6 @@ DefinitionBlock(
} }
} }
/* Chipset specific sleep states */
#include <southbridge/intel/common/acpi/sleepstates.asl> #include <southbridge/intel/common/acpi/sleepstates.asl>
} }

1
src/mainboard/intel/baskingridge/dsdt.asl
View File

@ -50,6 +50,5 @@ DefinitionBlock(
#include <vendorcode/google/chromeos/acpi/chromeos.asl> #include <vendorcode/google/chromeos/acpi/chromeos.asl>
/* Chipset specific sleep states */
#include <southbridge/intel/common/acpi/sleepstates.asl> #include <southbridge/intel/common/acpi/sleepstates.asl>
} }

1
src/mainboard/intel/cannonlake_rvp/dsdt.asl
View File

@ -43,7 +43,6 @@ DefinitionBlock(
#include <vendorcode/google/chromeos/acpi/chromeos.asl> #include <vendorcode/google/chromeos/acpi/chromeos.asl>
#endif #endif
// Chipset specific sleep states
#include <southbridge/intel/common/acpi/sleepstates.asl> #include <southbridge/intel/common/acpi/sleepstates.asl>
} }

1
src/mainboard/intel/coffeelake_rvp/dsdt.asl
View File

@ -43,7 +43,6 @@ DefinitionBlock(
#include <vendorcode/google/chromeos/acpi/chromeos.asl> #include <vendorcode/google/chromeos/acpi/chromeos.asl>
#endif #endif
// Chipset specific sleep states
#include <southbridge/intel/common/acpi/sleepstates.asl> #include <southbridge/intel/common/acpi/sleepstates.asl>
} }

1
src/mainboard/intel/d510mo/dsdt.asl
View File

@ -37,6 +37,5 @@ DefinitionBlock(
} }
} }
/* Chipset specific sleep states */
#include <southbridge/intel/common/acpi/sleepstates.asl> #include <southbridge/intel/common/acpi/sleepstates.asl>
} }

1
src/mainboard/intel/d945gclf/dsdt.asl
View File

@ -48,6 +48,5 @@ DefinitionBlock(
} }
} }
/* Chipset specific sleep states */
#include <southbridge/intel/common/acpi/sleepstates.asl> #include <southbridge/intel/common/acpi/sleepstates.asl>
} }

1
src/mainboard/intel/dg41wv/dsdt.asl
View File

@ -37,6 +37,5 @@ DefinitionBlock(
} }
} }
/* Chipset specific sleep states */
#include <southbridge/intel/common/acpi/sleepstates.asl> #include <southbridge/intel/common/acpi/sleepstates.asl>
} }

1
src/mainboard/intel/dg43gt/dsdt.asl
View File

@ -37,6 +37,5 @@ DefinitionBlock(
} }
} }
/* Chipset specific sleep states */
#include <southbridge/intel/common/acpi/sleepstates.asl> #include <southbridge/intel/common/acpi/sleepstates.asl>
} }

1
src/mainboard/intel/emeraldlake2/dsdt.asl
View File

@ -51,6 +51,5 @@ DefinitionBlock(
#include <vendorcode/google/chromeos/acpi/chromeos.asl> #include <vendorcode/google/chromeos/acpi/chromeos.asl>
/* Chipset specific sleep states */
#include <southbridge/intel/common/acpi/sleepstates.asl> #include <southbridge/intel/common/acpi/sleepstates.asl>
} }

1
src/mainboard/intel/glkrvp/dsdt.asl
View File

@ -44,7 +44,6 @@ DefinitionBlock(
/* Chrome OS specific */ /* Chrome OS specific */
#include <vendorcode/google/chromeos/acpi/chromeos.asl> #include <vendorcode/google/chromeos/acpi/chromeos.asl>
/* Chipset specific sleep states */
#include <southbridge/intel/common/acpi/sleepstates.asl> #include <southbridge/intel/common/acpi/sleepstates.asl>
/* Chrome OS Embedded Controller */ /* Chrome OS Embedded Controller */

1
src/mainboard/intel/harcuvar/dsdt.asl
View File

@ -49,6 +49,5 @@ DefinitionBlock(
} }
} }
/* Chipset specific sleep states */
#include <southbridge/intel/common/acpi/sleepstates.asl> #include <southbridge/intel/common/acpi/sleepstates.asl>
} }

1
src/mainboard/intel/icelake_rvp/dsdt.asl
View File

@ -58,7 +58,6 @@ DefinitionBlock(
} }
#endif #endif
// Chipset specific sleep states
#include <southbridge/intel/common/acpi/sleepstates.asl> #include <southbridge/intel/common/acpi/sleepstates.asl>
// Mainboard specific // Mainboard specific

1
src/mainboard/intel/kblrvp/dsdt.asl
View File

@ -55,7 +55,6 @@ DefinitionBlock(
#include <vendorcode/google/chromeos/acpi/chromeos.asl> #include <vendorcode/google/chromeos/acpi/chromeos.asl>
#endif #endif
// Chipset specific sleep states
#include <southbridge/intel/common/acpi/sleepstates.asl> #include <southbridge/intel/common/acpi/sleepstates.asl>
// Mainboard specific // Mainboard specific

1
src/mainboard/intel/kunimitsu/dsdt.asl
View File

@ -47,7 +47,6 @@ DefinitionBlock(
// Chrome OS specific // Chrome OS specific
#include <vendorcode/google/chromeos/acpi/chromeos.asl> #include <vendorcode/google/chromeos/acpi/chromeos.asl>
// Chipset specific sleep states
#include <southbridge/intel/common/acpi/sleepstates.asl> #include <southbridge/intel/common/acpi/sleepstates.asl>
// Mainboard specific // Mainboard specific

1
src/mainboard/intel/leafhill/dsdt.asl
View File

@ -38,6 +38,5 @@ DefinitionBlock(
} }
} }
/* Chipset specific sleep states */
#include <southbridge/intel/common/acpi/sleepstates.asl> #include <southbridge/intel/common/acpi/sleepstates.asl>
} }

1
src/mainboard/intel/minnow3/dsdt.asl
View File

@ -38,6 +38,5 @@ DefinitionBlock(
} }
} }
/* Chipset specific sleep states */
#include <southbridge/intel/common/acpi/sleepstates.asl> #include <southbridge/intel/common/acpi/sleepstates.asl>
} }

1
src/mainboard/intel/saddlebrook/dsdt.asl
View File

@ -41,7 +41,6 @@ DefinitionBlock(
} }
} }
// Chipset specific sleep states
#include <southbridge/intel/common/acpi/sleepstates.asl> #include <southbridge/intel/common/acpi/sleepstates.asl>
// Mainboard specific // Mainboard specific

1
src/mainboard/intel/strago/dsdt.asl
View File

@ -56,7 +56,6 @@ DefinitionBlock(
} }
#include <vendorcode/google/chromeos/acpi/chromeos.asl> #include <vendorcode/google/chromeos/acpi/chromeos.asl>
/* Chipset specific sleep states */
#include <southbridge/intel/common/acpi/sleepstates.asl> #include <southbridge/intel/common/acpi/sleepstates.asl>
#include "acpi/mainboard.asl" #include "acpi/mainboard.asl"

1
src/mainboard/intel/wtm2/dsdt.asl
View File

@ -53,7 +53,6 @@ DefinitionBlock(
// Chrome OS specific // Chrome OS specific
#include <vendorcode/google/chromeos/acpi/chromeos.asl> #include <vendorcode/google/chromeos/acpi/chromeos.asl>
// Chipset specific sleep states
#include <southbridge/intel/common/acpi/sleepstates.asl> #include <southbridge/intel/common/acpi/sleepstates.asl>
// Mainboard specific // Mainboard specific

1
src/mainboard/kontron/986lcd-m/dsdt.asl
View File

@ -44,6 +44,5 @@ DefinitionBlock(
} }
} }
/* Chipset specific sleep states */
#include <southbridge/intel/common/acpi/sleepstates.asl> #include <southbridge/intel/common/acpi/sleepstates.asl>
} }

1
src/mainboard/kontron/ktqm77/dsdt.asl
View File

@ -50,6 +50,5 @@ DefinitionBlock(
} }
} }
/* Chipset specific sleep states */
#include <southbridge/intel/common/acpi/sleepstates.asl> #include <southbridge/intel/common/acpi/sleepstates.asl>
} }

1
src/mainboard/lenovo/t400/dsdt.asl
View File

@ -51,7 +51,6 @@ DefinitionBlock(
} }
} }
/* Chipset specific sleep states */
#include <southbridge/intel/common/acpi/sleepstates.asl> #include <southbridge/intel/common/acpi/sleepstates.asl>
/* Hybrid graphics support code */ /* Hybrid graphics support code */

1
src/mainboard/lenovo/t410/dsdt.asl
View File

@ -85,7 +85,6 @@ DefinitionBlock(
} }
} }
/* Chipset specific sleep states */
#include <southbridge/intel/common/acpi/sleepstates.asl> #include <southbridge/intel/common/acpi/sleepstates.asl>
/* Dock support code */ /* Dock support code */

1
src/mainboard/lenovo/t420/dsdt.asl
View File

@ -50,6 +50,5 @@ DefinitionBlock(
} }
} }
/* Chipset specific sleep states */
#include <southbridge/intel/common/acpi/sleepstates.asl> #include <southbridge/intel/common/acpi/sleepstates.asl>
} }

1
src/mainboard/lenovo/t420s/dsdt.asl
View File

@ -50,6 +50,5 @@ DefinitionBlock(
} }
} }
/* Chipset specific sleep states */
#include <southbridge/intel/common/acpi/sleepstates.asl> #include <southbridge/intel/common/acpi/sleepstates.asl>
} }

1
src/mainboard/lenovo/t430s/dsdt.asl
View File

@ -50,6 +50,5 @@ DefinitionBlock(
} }
} }
/* Chipset specific sleep states */
#include <southbridge/intel/common/acpi/sleepstates.asl> #include <southbridge/intel/common/acpi/sleepstates.asl>
} }

1
src/mainboard/lenovo/t520/dsdt.asl
View File

@ -50,6 +50,5 @@ DefinitionBlock(
} }
} }
/* Chipset specific sleep states */
#include <southbridge/intel/common/acpi/sleepstates.asl> #include <southbridge/intel/common/acpi/sleepstates.asl>
} }

1
src/mainboard/lenovo/t530/dsdt.asl
View File

@ -50,6 +50,5 @@ DefinitionBlock(
} }
} }
/* Chipset specific sleep states */
#include <southbridge/intel/common/acpi/sleepstates.asl> #include <southbridge/intel/common/acpi/sleepstates.asl>
} }

1
src/mainboard/lenovo/t60/dsdt.asl
View File

@ -57,7 +57,6 @@ DefinitionBlock(
} }
} }
/* Chipset specific sleep states */
#include <southbridge/intel/common/acpi/sleepstates.asl> #include <southbridge/intel/common/acpi/sleepstates.asl>
// Dock support code // Dock support code

1
src/mainboard/lenovo/thinkcentre_a58/dsdt.asl
View File

@ -37,6 +37,5 @@ DefinitionBlock(
} }
} }
/* Chipset specific sleep states */
#include <southbridge/intel/common/acpi/sleepstates.asl> #include <southbridge/intel/common/acpi/sleepstates.asl>
} }

1
src/mainboard/lenovo/x131e/dsdt.asl
View File

@ -39,7 +39,6 @@ DefinitionBlock(
// global NVS and variables // global NVS and variables
#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
// Chipset specific sleep states
#include <southbridge/intel/common/acpi/sleepstates.asl> #include <southbridge/intel/common/acpi/sleepstates.asl>
Scope (\_SB) { Scope (\_SB) {

1
src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl
View File

@ -50,6 +50,5 @@ DefinitionBlock(
} }
} }
/* Chipset specific sleep states */
#include <southbridge/intel/common/acpi/sleepstates.asl> #include <southbridge/intel/common/acpi/sleepstates.asl>
} }

1
src/mainboard/lenovo/x200/dsdt.asl
View File

@ -50,7 +50,6 @@ DefinitionBlock(
} }
} }
/* Chipset specific sleep states */
#include <southbridge/intel/common/acpi/sleepstates.asl> #include <southbridge/intel/common/acpi/sleepstates.asl>
/* Dock support code */ /* Dock support code */

1
src/mainboard/lenovo/x201/dsdt.asl
View File

@ -85,7 +85,6 @@ DefinitionBlock(
} }
} }
/* Chipset specific sleep states */
#include <southbridge/intel/common/acpi/sleepstates.asl> #include <southbridge/intel/common/acpi/sleepstates.asl>
/* Dock support code */ /* Dock support code */

1
src/mainboard/lenovo/x220/dsdt.asl
View File

@ -50,6 +50,5 @@ DefinitionBlock(
} }
} }
/* Chipset specific sleep states */
#include <southbridge/intel/common/acpi/sleepstates.asl> #include <southbridge/intel/common/acpi/sleepstates.asl>
} }

1
src/mainboard/lenovo/x230/dsdt.asl
View File

@ -50,6 +50,5 @@ DefinitionBlock(
} }
} }
/* Chipset specific sleep states */
#include <southbridge/intel/common/acpi/sleepstates.asl> #include <southbridge/intel/common/acpi/sleepstates.asl>
} }

1
src/mainboard/lenovo/x60/dsdt.asl
View File

@ -51,7 +51,6 @@ DefinitionBlock(
} }
} }
/* Chipset specific sleep states */
#include <southbridge/intel/common/acpi/sleepstates.asl> #include <southbridge/intel/common/acpi/sleepstates.asl>
// Dock support code // Dock support code

1
src/mainboard/packardbell/ms2290/dsdt.asl
View File

@ -79,6 +79,5 @@ DefinitionBlock(
} }
} }
/* Chipset specific sleep states */
#include <southbridge/intel/common/acpi/sleepstates.asl> #include <southbridge/intel/common/acpi/sleepstates.asl>
} }

2
src/mainboard/portwell/m107/dsdt.asl
View File

@ -43,7 +43,7 @@ DefinitionBlock(
} }
} }
/* Chipset specific sleep states */ /* Mainboard specific sleep states */
#include "acpi/sleepstates.asl" #include "acpi/sleepstates.asl"
#include "acpi/mainboard.asl" #include "acpi/mainboard.asl"
} }

1
src/mainboard/purism/librem_bdw/dsdt.asl
View File

@ -39,7 +39,6 @@ DefinitionBlock(
} }
} }
/* Chipset specific sleep states */
#include <southbridge/intel/common/acpi/sleepstates.asl> #include <southbridge/intel/common/acpi/sleepstates.asl>
/* Mainboard specific */ /* Mainboard specific */

1
src/mainboard/purism/librem_skl/dsdt.asl
View File

@ -42,7 +42,6 @@ DefinitionBlock(
} }
// Chipset specific sleep states
#include <southbridge/intel/common/acpi/sleepstates.asl> #include <southbridge/intel/common/acpi/sleepstates.asl>
// Mainboard specific // Mainboard specific

2
src/mainboard/razer/blade_stealth_kbl/dsdt.asl
View File

@ -42,7 +42,7 @@ DefinitionBlock(
} }
} }
// Chipset specific sleep states
#include <southbridge/intel/common/acpi/sleepstates.asl> #include <southbridge/intel/common/acpi/sleepstates.asl>
#include "acpi/mainboard.asl" #include "acpi/mainboard.asl"

1
src/mainboard/roda/rk886ex/dsdt.asl
View File

@ -49,6 +49,5 @@ DefinitionBlock(
} }
} }
/* Chipset specific sleep states */
#include <southbridge/intel/common/acpi/sleepstates.asl> #include <southbridge/intel/common/acpi/sleepstates.asl>
} }

1
src/mainboard/roda/rk9/dsdt.asl
View File

@ -51,6 +51,5 @@ DefinitionBlock(
} }
} }
/* Chipset specific sleep states */
#include <southbridge/intel/common/acpi/sleepstates.asl> #include <southbridge/intel/common/acpi/sleepstates.asl>
} }

1
src/mainboard/roda/rv11/dsdt.asl
View File

@ -48,6 +48,5 @@ DefinitionBlock(
} }
} }
/* Chipset specific sleep states */
#include <southbridge/intel/common/acpi/sleepstates.asl> #include <southbridge/intel/common/acpi/sleepstates.asl>
} }

1
src/mainboard/samsung/lumpy/dsdt.asl
View File

@ -54,6 +54,5 @@ DefinitionBlock(
#include <vendorcode/google/chromeos/acpi/chromeos.asl> #include <vendorcode/google/chromeos/acpi/chromeos.asl>
/* Chipset specific sleep states */
#include <southbridge/intel/common/acpi/sleepstates.asl> #include <southbridge/intel/common/acpi/sleepstates.asl>
} }

1
src/mainboard/samsung/stumpy/dsdt.asl
View File

@ -51,6 +51,5 @@ DefinitionBlock(
#include <vendorcode/google/chromeos/acpi/chromeos.asl> #include <vendorcode/google/chromeos/acpi/chromeos.asl>
/* Chipset specific sleep states */
#include <southbridge/intel/common/acpi/sleepstates.asl> #include <southbridge/intel/common/acpi/sleepstates.asl>
} }

1
src/mainboard/scaleway/tagada/dsdt.asl
View File

@ -49,6 +49,5 @@ DefinitionBlock(
} }
} }
/* Chipset specific sleep states */
#include <southbridge/intel/common/acpi/sleepstates.asl> #include <southbridge/intel/common/acpi/sleepstates.asl>
} }

1
src/mainboard/siemens/mc_apl1/dsdt.asl
View File

@ -40,6 +40,5 @@ DefinitionBlock(
} }
} }
/* Chipset specific sleep states */
#include <southbridge/intel/common/acpi/sleepstates.asl> #include <southbridge/intel/common/acpi/sleepstates.asl>
} }

1
src/mainboard/supermicro/x11-lga1151-series/dsdt.asl
View File

@ -41,7 +41,6 @@ DefinitionBlock(
} }
} }
// Chipset specific sleep states
#include <southbridge/intel/common/acpi/sleepstates.asl> #include <southbridge/intel/common/acpi/sleepstates.asl>
// Mainboard specific // Mainboard specific

1
src/mainboard/up/squared/dsdt.asl
View File

@ -38,6 +38,5 @@ DefinitionBlock(
} }
} }
/* Chipset specific sleep states */
#include <southbridge/intel/common/acpi/sleepstates.asl> #include <southbridge/intel/common/acpi/sleepstates.asl>
} }