From 408d3928236f275633f8656cc12e32949d304d9f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Fri, 17 Jun 2016 10:43:48 +0300 Subject: [PATCH] intel/car/cache_as_ram_ht.inc: Prepare for dynamic CONFIG_RAMTOP MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Idb0f621553e76e771a5d6f2d492675ccd989d947 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/15228 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/cpu/intel/car/cache_as_ram_ht.inc | 11 ++++++++--- src/cpu/intel/model_106cx/Makefile.inc | 1 + src/cpu/intel/socket_LGA775/Makefile.inc | 1 + src/cpu/intel/socket_mPGA604/Makefile.inc | 1 + src/mainboard/aopen/dxplplusu/romstage.c | 4 ++-- src/mainboard/gigabyte/ga-g41m-es2l/romstage.c | 4 ++-- src/mainboard/intel/d510mo/romstage.c | 4 ++-- src/mainboard/intel/d945gclf/romstage.c | 4 ++-- src/mainboard/iwave/iWRainbowG6/romstage.c | 4 ++-- 9 files changed, 21 insertions(+), 13 deletions(-) diff --git a/src/cpu/intel/car/cache_as_ram_ht.inc b/src/cpu/intel/car/cache_as_ram_ht.inc index ee4a1bb332..f5256adb76 100644 --- a/src/cpu/intel/car/cache_as_ram_ht.inc +++ b/src/cpu/intel/car/cache_as_ram_ht.inc @@ -339,8 +339,12 @@ no_msr_11e: post_code(0x2f) /* Call romstage.c main function. */ - call main - addl $4, %esp + call romstage_main + + /* Save return value from romstage_main. It contains the stack to use + * after cache-as-ram is torn down. It also contains the information + * for setting up MTRRs. */ + movl %eax, %ebx post_code(0x30) @@ -425,7 +429,8 @@ __main: post_code(POST_PREPARE_RAMSTAGE) cld /* Clear direction flag. */ - movl $CONFIG_RAMTOP, %esp + /* Setup stack as indicated by return value from romstage_main(). */ + movl %ebx, %esp movl %esp, %ebp call copy_and_run diff --git a/src/cpu/intel/model_106cx/Makefile.inc b/src/cpu/intel/model_106cx/Makefile.inc index 25631e5d36..d15c362dc0 100644 --- a/src/cpu/intel/model_106cx/Makefile.inc +++ b/src/cpu/intel/model_106cx/Makefile.inc @@ -2,4 +2,5 @@ ramstage-y += model_106cx_init.c subdirs-y += ../../x86/name cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram_ht.inc +romstage-y += ../car/romstage.c cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_106cx/microcode.bin diff --git a/src/cpu/intel/socket_LGA775/Makefile.inc b/src/cpu/intel/socket_LGA775/Makefile.inc index af57eda762..54a762eb44 100644 --- a/src/cpu/intel/socket_LGA775/Makefile.inc +++ b/src/cpu/intel/socket_LGA775/Makefile.inc @@ -15,3 +15,4 @@ subdirs-y += ../hyperthreading subdirs-y += ../speedstep cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram_ht.inc +romstage-y += ../car/romstage.c diff --git a/src/cpu/intel/socket_mPGA604/Makefile.inc b/src/cpu/intel/socket_mPGA604/Makefile.inc index 4548f3d46d..98306d4fa6 100644 --- a/src/cpu/intel/socket_mPGA604/Makefile.inc +++ b/src/cpu/intel/socket_mPGA604/Makefile.inc @@ -10,3 +10,4 @@ subdirs-y += ../microcode subdirs-y += ../hyperthreading cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram_ht.inc +romstage-y += ../car/romstage.c diff --git a/src/mainboard/aopen/dxplplusu/romstage.c b/src/mainboard/aopen/dxplplusu/romstage.c index 1e78a979a3..5e7a15958a 100644 --- a/src/mainboard/aopen/dxplplusu/romstage.c +++ b/src/mainboard/aopen/dxplplusu/romstage.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include @@ -34,8 +35,7 @@ int spd_read_byte(unsigned device, unsigned address) return smbus_read_byte(device, address); } -#include -void main(unsigned long bist) +void mainboard_romstage_entry(unsigned long bist) { static const struct mem_controller memctrl[] = { { diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c index 63654047fd..b6be8fba7a 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c +++ b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c @@ -23,10 +23,10 @@ #include #include #include +#include #include #include #include -#include #include #include @@ -132,7 +132,7 @@ static void ich7_enable_lpc(void) pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8a, 0x007c); } -void main(unsigned long bist) +void mainboard_romstage_entry(unsigned long bist) { // ch0 ch1 const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 }; diff --git a/src/mainboard/intel/d510mo/romstage.c b/src/mainboard/intel/d510mo/romstage.c index 28481c026f..f73bf649a9 100644 --- a/src/mainboard/intel/d510mo/romstage.c +++ b/src/mainboard/intel/d510mo/romstage.c @@ -24,6 +24,7 @@ #include #include #include +#include #include #include #include @@ -33,7 +34,6 @@ #define SERIAL_DEV PNP_DEV(0x4e, W83627THG_SP1) #define SUPERIO_DEV PNP_DEV(0x4e, 0) -#include /* Early mainboard specific GPIO setup */ static void mb_gpio_init(void) @@ -102,7 +102,7 @@ static void rcba_config(void) RCBA32(0x3418) |= 1; } -void main(unsigned long bist) +void mainboard_romstage_entry(unsigned long bist) { const u8 spd_addrmap[4] = { 0x50, 0x51, 0, 0 }; diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c index f46cdc03c6..8077ba212d 100644 --- a/src/mainboard/intel/d945gclf/romstage.c +++ b/src/mainboard/intel/d945gclf/romstage.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include #include @@ -149,8 +150,7 @@ static void early_ich7_init(void) RCBA32(0x2034) = reg32; } -#include -void main(unsigned long bist) +void mainboard_romstage_entry(unsigned long bist) { int s3resume = 0, boot_mode = 0; diff --git a/src/mainboard/iwave/iWRainbowG6/romstage.c b/src/mainboard/iwave/iWRainbowG6/romstage.c index 37b442c0be..a6c5a715c3 100644 --- a/src/mainboard/iwave/iWRainbowG6/romstage.c +++ b/src/mainboard/iwave/iWRainbowG6/romstage.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include #if 0 @@ -328,8 +329,7 @@ static void poulsbo_setup_Stage2Regs(void) printk(BIOS_DEBUG, " done.\n"); } -#include -void main(unsigned long bist) +void mainboard_romstage_entry(unsigned long bist) { int boot_mode = 0;