Update amd/south_station/fadt.c with various fixes
This is a model fadt.c that I would like to use for updating several other AMD platforms with after acceptance. - Updated to match ACPI 3.0b specification and added comments to reflect that. - Since smi_cmd is 0, remove commands that rely on it: acpi_enable, acpi_disable, & pstate_cnt Add comments to that effect. - Changed preferred_pm_profile to SOHO Server (platform specific) - The southstation platform is legacy free - Updated iapc_boot_arch and flags to reflect that. - Added reset_register flag so that operating systems will actually use the reset_reg. This is important on legacy free systems. - Updated Generic Address Structures to use access_size name in the updated acpi.h. Added access sizes to the structures where reasonable. - Removed 64-bit x_firmware_ctl pointer to facs. This was causing a fwts failure and windows-64 BSOD. - Added bit width for pm2_cnt_blk and modified gpe0_blk bit to match the hardware. Change-Id: Icf1a982aa122636d1088c8b80f53d04732b54c49 Signed-off-by: Martin L Roth <martin@se-eng.com> Reviewed-on: http://review.coreboot.org/942 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
This commit is contained in:
Martin Roth
Marc Jones
parent
a293714579
commit
40aa9bce7d
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@ -30,17 +30,23 @@
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#include <device/device.h>
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#include "SBPLATFORM.h"
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/*
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* Reference section 5.2.9 Fixed ACPI Description Table (FADT)
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* in the ACPI 3.0b specification.
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*/
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void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
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{
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u16 val = 0;
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acpi_header_t *header = &(fadt->header);
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printk(BIOS_DEBUG, "ACPI_BLK_BASE: 0x%04x\n", ACPI_BLK_BASE);
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/* Prepare the header */
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memset((void *)fadt, 0, sizeof(acpi_fadt_t));
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memcpy(header->signature, "FACP", 4);
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header->length = 244;
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header->revision = 3;
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header->length = sizeof(acpi_fadt_t);
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header->revision = ACPI_FADT_REV_ACPI_3_0;
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memcpy(header->oem_id, OEM_ID, 6);
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memcpy(header->oem_table_id, "COREBOOT", 8);
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memcpy(header->asl_compiler_id, ASLC, 4);
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@ -48,15 +54,14 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
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fadt->firmware_ctrl = (u32) facs;
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fadt->dsdt = (u32) dsdt;
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/* 3=Workstation,4=Enterprise Server, 7=Performance Server */
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fadt->preferred_pm_profile = 0x03;
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fadt->sci_int = 9;
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/* disable system management mode by setting to 0: */
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fadt->smi_cmd = 0;
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fadt->acpi_enable = 0xf0;
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fadt->acpi_disable = 0xf1;
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fadt->s4bios_req = 0x0;
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fadt->pstate_cnt = 0xe2;
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fadt->model = 0; /* reserved, should be 0 ACPI 3.0 */
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fadt->preferred_pm_profile = PM_SOHO_SERVER;
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fadt->sci_int = 9; /* HUDSON 1 - IRQ 09 – ACPI SCI */
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fadt->smi_cmd = 0; /* disable system management mode */
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fadt->acpi_enable = 0; /* unused if SMI_CMD = 0 */
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fadt->acpi_disable = 0; /* unused if SMI_CMD = 0 */
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fadt->s4bios_req = 0; /* unused if SMI_CMD = 0 */
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fadt->pstate_cnt = 0; /* unused if SMI_CMD = 0 */
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val = PM1_EVT_BLK_ADDRESS;
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WritePMIO(SB_PMIOA_REG60, AccWidthUint16, &val);
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@ -90,7 +95,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
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fadt->pm2_cnt_blk = ACPI_PMA_CNT_BLK_ADDRESS;
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fadt->pm_tmr_blk = PM1_TMR_BLK_ADDRESS;
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fadt->gpe0_blk = GPE0_BLK_ADDRESS;
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fadt->gpe1_blk = 0x0000; /* we dont have gpe1 block, do we? */
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fadt->gpe1_blk = 0; /* No gpe1 block in hudson1 */
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fadt->pm1_evt_len = 4;
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fadt->pm1_cnt_len = 2;
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@ -103,89 +108,103 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
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fadt->cst_cnt = 0xe3;
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fadt->p_lvl2_lat = 101;
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fadt->p_lvl3_lat = 1001;
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fadt->flush_size = 0;
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fadt->flush_stride = 0;
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fadt->flush_size = 0; /* set to 0 if WBINVD is 1 in flags */
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fadt->flush_stride = 0; /* set to 0 if WBINVD is 1 in flags */
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fadt->duty_offset = 1;
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fadt->duty_width = 3;
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fadt->day_alrm = 0; /* 0x7d these have to be */
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fadt->mon_alrm = 0; /* 0x7e added to cmos.layout */
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fadt->century = 0; /* 0x7f to make rtc alrm work */
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fadt->iapc_boot_arch = 0x3; /* See table 5-11 */
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fadt->flags = 0x0001c1a5;/* 0x25; */
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fadt->iapc_boot_arch = ACPI_FADT_LEGACY_FREE; /* See table 5-10 */
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fadt->res2 = 0; /* reserved, MUST be 0 ACPI 3.0 */
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fadt->flags = ACPI_FADT_WBINVD | /* See table 5-10 ACPI 3.0a spec */
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ACPI_FADT_C1_SUPPORTED |
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ACPI_FADT_SLEEP_BUTTON |
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ACPI_FADT_S4_RTC_WAKE |
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ACPI_FADT_32BIT_TIMER |
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ACPI_FADT_RESET_REGISTER |
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ACPI_FADT_PCI_EXPRESS_WAKE |
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ACPI_FADT_S4_RTC_VALID |
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ACPI_FADT_REMOTE_POWER_ON;
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fadt->res2 = 0;
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fadt->reset_reg.space_id = 1;
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/* Format is from 5.2.3.1: Generic Address Structure */
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/* reset_reg: see section 4.7.3.6 ACPI 3.0a spec */
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/* 8 bit write of value 0x06 to 0xCF9 in IO space */
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fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO;
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fadt->reset_reg.bit_width = 8;
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fadt->reset_reg.bit_offset = 0;
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fadt->reset_reg.resv = 0;
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fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
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fadt->reset_reg.addrl = 0xcf9;
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fadt->reset_reg.addrh = 0x0;
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fadt->reset_value = 6;
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fadt->x_firmware_ctl_l = (u32) facs;
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fadt->res3 = 0; /* reserved, MUST be 0 ACPI 3.0 */
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fadt->res4 = 0; /* reserved, MUST be 0 ACPI 3.0 */
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fadt->res5 = 0; /* reserved, MUST be 0 ACPI 3.0 */
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fadt->x_firmware_ctl_l = 0; /* set to 0 if firmware_ctrl is used */
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fadt->x_firmware_ctl_h = 0;
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fadt->x_dsdt_l = (u32) dsdt;
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fadt->x_dsdt_h = 0;
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fadt->x_pm1a_evt_blk.space_id = 1;
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fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
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fadt->x_pm1a_evt_blk.bit_width = 32;
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fadt->x_pm1a_evt_blk.bit_offset = 0;
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fadt->x_pm1a_evt_blk.resv = 0;
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fadt->x_pm1a_evt_blk.access_size = 0;
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fadt->x_pm1a_evt_blk.addrl = PM1_EVT_BLK_ADDRESS;
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fadt->x_pm1a_evt_blk.addrh = 0x0;
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fadt->x_pm1b_evt_blk.space_id = 1;
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fadt->x_pm1b_evt_blk.bit_width = 4;
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fadt->x_pm1b_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
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fadt->x_pm1b_evt_blk.bit_width = 0;
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fadt->x_pm1b_evt_blk.bit_offset = 0;
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fadt->x_pm1b_evt_blk.resv = 0;
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fadt->x_pm1b_evt_blk.access_size = 0;
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fadt->x_pm1b_evt_blk.addrl = 0x0;
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fadt->x_pm1b_evt_blk.addrh = 0x0;
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fadt->x_pm1a_cnt_blk.space_id = 1;
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fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
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fadt->x_pm1a_cnt_blk.bit_width = 16;
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fadt->x_pm1a_cnt_blk.bit_offset = 0;
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fadt->x_pm1a_cnt_blk.resv = 0;
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fadt->x_pm1a_cnt_blk.access_size = 0;
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fadt->x_pm1a_cnt_blk.addrl = PM1_CNT_BLK_ADDRESS;
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fadt->x_pm1a_cnt_blk.addrh = 0x0;
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fadt->x_pm1b_cnt_blk.space_id = 1;
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fadt->x_pm1b_cnt_blk.bit_width = 2;
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fadt->x_pm1b_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
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fadt->x_pm1b_cnt_blk.bit_width = 0;
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fadt->x_pm1b_cnt_blk.bit_offset = 0;
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fadt->x_pm1b_cnt_blk.resv = 0;
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fadt->x_pm1b_cnt_blk.access_size = 0;
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fadt->x_pm1b_cnt_blk.addrl = 0x0;
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fadt->x_pm1b_cnt_blk.addrh = 0x0;
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fadt->x_pm2_cnt_blk.space_id = 1;
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fadt->x_pm2_cnt_blk.bit_width = 0;
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fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
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fadt->x_pm2_cnt_blk.bit_width = 8; /* Hudson 1 Pm2Control is 8 bits */
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fadt->x_pm2_cnt_blk.bit_offset = 0;
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fadt->x_pm2_cnt_blk.resv = 0;
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fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
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fadt->x_pm2_cnt_blk.addrl = ACPI_PMA_CNT_BLK_ADDRESS;
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fadt->x_pm2_cnt_blk.addrh = 0x0;
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fadt->x_pm_tmr_blk.space_id = 1;
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fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO;
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fadt->x_pm_tmr_blk.bit_width = 32;
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fadt->x_pm_tmr_blk.bit_offset = 0;
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fadt->x_pm_tmr_blk.resv = 0;
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fadt->x_pm_tmr_blk.access_size = 0;
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fadt->x_pm_tmr_blk.addrl = PM1_TMR_BLK_ADDRESS;
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fadt->x_pm_tmr_blk.addrh = 0x0;
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fadt->x_gpe0_blk.space_id = 1;
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fadt->x_gpe0_blk.bit_width = 32;
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fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO;
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fadt->x_gpe0_blk.bit_width = 64;
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fadt->x_gpe0_blk.bit_offset = 0;
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fadt->x_gpe0_blk.resv = 0;
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fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
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fadt->x_gpe0_blk.addrl = GPE0_BLK_ADDRESS;
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fadt->x_gpe0_blk.addrh = 0x0;
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fadt->x_gpe1_blk.space_id = 1;
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fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_IO;
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fadt->x_gpe1_blk.bit_width = 0;
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fadt->x_gpe1_blk.bit_offset = 0;
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fadt->x_gpe1_blk.resv = 0;
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fadt->x_gpe1_blk.access_size = 0;
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fadt->x_gpe1_blk.addrl = 0;
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fadt->x_gpe1_blk.addrh = 0x0;
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